ChipPAC Stacks Chips
News Analysis
ChipPAC announced that its 3-die-stacked assembly technology has been qualified and is shipping to customers now. The 3-die system-in-package (SiP) is targeting 2.5G and 3G wireless applications. CDMA (3G) applications, for example, benefit from integrating ASIC, memory and controller chips, or two flash and one SRAM devices. To accomplish the 3-die-stack without increasing the package thickness compared to a 2-die stack, ChipPAC thins wafers to 140 microns. Marcos Karnezos, ChipPAC CTO, claims that they will be thinning wafers to 100 microns early in 2002. The current total package height for the 3-die-stack is 1.4 mm now, with 1.2 mm being the target for early 2002.
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