BY SANG HA KIM, AND HAN PARK, NEC ELECTRONICS AMERICA; AnD CHIKA KAKEGAWA, HIROSHI TABUCHI, MAMORU KAJIHARA, NEC ELECTRONICS CORP.
Challenges of high-end FCSiP include routability with acceptable signal and power integrity, package thermo-mechanical behaviors, and long term reliability performance. Data obtained from DOE analysis and an FEA case study defined critical factors to FCSiP solder joint fatigue and how to address them.
The development of high-density interconnection package has become important in fast-growing electronic industries such as server, network, and telecommunication applications. The flip chip system-in-package (FCSiP) can conduct higher electrical performance, reduce the size of system board, and also reduce the layer count in the system board by combining the advantages of flip chip and SiP technology.
 Figure 1. FCSiP configuration, a. topside view (without heat spreader) and b. cross section view. |
The FCSiP consists of one ASIC flip chip centered on the package, and four PBGA memory packages at the four corners of the SiP module (Figure 1). Flip chip ASIC and memory configuration in SiP requires fast operating frequency and higher bandwidth. The challenges of high-end FCSiP are routability with acceptable signal and power integrity, package thermo-mechanical behaviors, and long-term reliability performance.
The Experiment
A design of experiments (DOE) analysis was used to carry out finite element analaysis (FEA case studies) and predict optimized FCSiP construction and assembly material sets. A set of FEA models whose strain energy density had been calculated prior to the testing was used. The analysis was done with a set of models based on evaluation factors and levels.
To optimize the construction process and the combinations of the materials, the fatigue lifetime of the BGA solder joint was evaluated based on 2-D Anand’s visco-plastic non-linear model. A total of 8 runs were performed with the 2(5-2) ¼ partial factorial design of DOE. The reference temperature was set at 183