Semiconductor assembly and test service (SATS) houses, packaging foundries, and integrated device manufacturers (IDMs) are increasingly turning to wafer-level packaging (WLP) to address the demand for miniaturization, lower cost, enhanced functionality, and higher reliability in today’s personal digital devices. WLP technology involves packaging integrated circuits (ICs) at the wafer level instead of the traditional process of assembling the package of each individual die following the dicing process. WLP is a true chip-scale packaging (CSP) technology because the resulting package is nearly the same size as the die. As a result, WLP is viewed as a strategic technology investment by both SAT and IDM companies. Furthermore, WLP paves the way for true integration of device fabrication, packaging, test, and burn-in at the wafer level to enable significant streamlining of the device manufacturing process, from silicon start to device shipment.

By Gail Flower, Editor-in-Chief