Yield losses in sub-100-nm processes include functional defects, performance problems, excessive leakage, and problems with testing. Problems such as capacitance, inductance, resistance, and cross-talk disrupt efforts to produce right-first-time silicon for timing and power budgets in sub-100-nm processes. ARC’s tool reportedly enables system-on-chip (SoC) designers to create ARC processor core designs for specific applications without increased complexity or risk. CPU/DSP processors and media-centric subsystems allow for less power and fewer transistor gates. Features include a drag-and-drop graphic user interface (GUI), and configuration options for type and size of caches, interrupts, core registers, and address bus widths. The tool offers performance and die-size tradeoff solutions for nano-processes. Its verified register-transfer-level (RTL) and synthesis scripts are compatible with the Encounter design flow.

Hah! I was RIGHT! Long before I knew anything about advanced packaging or the inner workings of a cell phone, I figured that the reason my two-year-old, bottom-of-the-line, no-bells-and-whistles cell phone got better reception than my friends’ newer, smaller flip phones &#151 equipped with cameras, color displays, and MP3 players &#151 had something to do with all that extra stuff, and not just the cell service in the Northeast.