(June 10, 2005) Norwalk, Conn. &#8212 The North American semiconductor dielectric materials market is estimated at $107 million in 2005, and is forecasted to grow at an average annual growth rate (AAGR) of 7.3% to $152 million by 2010. During the same period, the global market is expected to increase from $597 million in 2005 to $1,012 million by 2010, according to a forthcoming report, RGB-243R Evolving Dielectrics in Semiconductor Devices, from Business Communications Co., Inc., (www.bccresearch.com).

(June 13, 2005) Geneva, Switzerland &#8212 Due to 5 years of research and development, STMicroelectronics has published a book on a novel chip design methodology. In their efforts, the authors of Transaction-Level Modeling with SystemC have paved the way for the next level of abstraction for production digital designs, yielding significant improvements in productivity and first-time silicon success. This modeling concept is supported by the newly released transaction-level modeling (TLM) library standard by the Open SystemC Initiative (OSCI), currently being introduced at the Design Automation Conference in Anaheim, Calif., running June 13-17.

Since system-on-chips (SoCs) are growing in complexity and embedded software is growing in proportion, new design methodologies are needed. Transaction-Level Modeling bridges the gap between design productivity and process capacity by raising the level of abstraction in specifying and modeling an SoC design. The book, Transaction-Level Modeling with SystemC, authored by an advanced R&D team from STMicroelectronics, presents an approach to resolve critical system-level issues in today’s complex digital designs.

ST’s TLM solution, based on the open-source SystemC modeling language, accommodates early embedded software development, functional verification, and performance analysis. Employed as the executable functional specification to compare against the Register-Transfer-Level (RTL), untimed TLM models are also assembled to build virtual prototype to develop significant software in parallel with hardware design. When complemented with timing information, the same models serve the needs of architecture analysis to ensure the compliance of an SoC design with real-time constraints of the targeted application.

The new abstraction level also provides a single functional reference that is shared between software, hardware, and system-level engineers. Sharing this executable specification removes ambiguity, duplication of information, and helps to detect architecture flaws before the modification cost becomes too high. These capabilities are said to allow reduction in design times up to 50% over previous methodologies, and help prevent silicon re-spins.

“We are witnessing a real paradigm shift in the way software and hardware engineers work with each other,” says Philippe Magarshack, group VP of Central R&D at STMicroelectronics. “TLM allows us to deliver a prototype to customers before the RTL is frozen, and therefore cuts time-to-market on a previously unattainable scale.”