OCT. 30–SANTA CLARA, CA–Advanced Semiconductor Engineering Inc. (ASE) says its 300 mm wafer flip chip bumping line is ready for production.

ASE completed its 300 mm wafer solder bumping technology in November 2001 and installed a fully automated bumping line the following December.

Despite the current downturn, chipmakers and foundries continue to invest in 300 mm wafer fabs.

According to Semico Research Corp.’s recent report, 300 mm capability will grow during the next few years to about 45% of total wafer production by the year 2006.

The migration to 300 mm wafers have been largely due to the increased difficulties of reducing per-die costs with shrinking feature size. 300 mm wafers will benefit complex, high end logic devices such as MPUs, DSPs, ASICs and FPGAs whereby savings can be achieved in per-die production cost.

Wafer bumping is an essential process for flip chip packaging, and ASE’s wafer bumping technology has been applied on 150mm and 200mm wafers for many years. Its 200mm wafer bumping technology has consistently attained a yield rate of 99% at a monthly output of 20,000 wafers and is qualified by major IDMs (independent device manufacturers).

“With industry migration to 300mm, ASE is already moving ahead by establishing processes and equipment to handle these larger wafers,” says J.J. Lee, vice president of ASE’s research and development.