May 21, 2007 — Potential solutions are starting to emerge for preparing wafers for manufacturing at and beyond the 45 nm technology generation, technologists indicated at a recent industry meeting organized by SEMATECH .

The 2007 Surface Preparation and Cleaning Conference reported several techniques for non-damaging particle removal from wafer surfaces, along with multiple methods for removing photoresist with minimal silicon and oxide loss.

“The 45 nm generation is coming up fast – and some chip-makers are there already – and many of the manufacturing issues are connected to surface preparation and cleaning,” said SEMATECH’s Joel Barnett, conference chair. “The conference made it clear that many of our chemistries and approaches will have to change, but that plenty of potential solutions are being considered for 45 nm and beyond.”

Twelve presentations covered non-damaging nanoparticle removal, and seven offered new or enhanced methods for minimizing silicon and oxide loss during photoresist removal.