By Sandra L. Winkler, New Venture Research

Itty bitty computers, smart phones, ipods, and more – these “must have” small electronic devices that Apple Computer and other companies have popularized, are forcing the hand of IC package designers to shrink the package to fit within these little hand-held gadgets.

Shrinking the package can be a challenge, as is routing these devices to a PCB.  Creative package designs, such as stacked packages, SiPs, and interconnection methods of through silicon vias (TSVs) are all being put into play to achieve a small footprint, enhanced electrical performance, while consuming less battery power.  Information on those technologies can be found in New Venture Research’s Advanced IC Packaging, Technologies, Materials, and Markets, 2012 Edition.

Package Pitch

Another method of reducing the form factor and reduced signal length is to reduce the package pitch, or the distance between the center of one second-level interconnect to the other as the interconnect to the printed circuit board (PCB).  The package pitch of a device, combined with the I/O count, will determine the size of a package substrate or leadframe, the test socket size, and the footprint of the device on a PCB.

Reducing the pitch on an IC package often results in smaller solder balls on an array package, and will require that the electrical traces to the package on the PCB be closer together.

When a package pitch is altered, this will in turn have an effect on the PCB layout, the solder ball size where applicable and volume of solder paste, the test socket and DUT board, and all the parts used to make the package itself.

When combining the total packages together, the pitch of 0.4 mm has the largest growth of all the pitch sizes, while the 0.5-mm pitch comprises the largest single package pitch. Figure 1 displays the percentages of these pitches for the years 2012 versus 2017.

Figure 1 Total IC Package Pitch Forecast, 2012 vs. 2017
(Click to view full screen.)