The next major roadblock to progress in the ongoing push to develop EUV lithography for volume production is the availability of defect-free mask blanks.

Pete Singer, Editor-in-Chief

FIGURE 1. A small pit on the substrate surfaces gets magnified through the multilayer stack.

According to Veeco’s Tim Pratt, Senior Director, Marketing, the tools in place today are not capable of producing mask blanks with the kind of yield necessary to support a ramp in EUV. “Based on the yield today, the mask blank manufacturing capacity can’t produce enough mask blanks to support the ASML scanners that they’re planning to ship,” Pratt said.

The requirement for 2015 is to have zero blank defects larger than 62nm. SEMATECH in 2012 reported work showing eight defects larger than 50nm. “A lot of progress being made but the elusive zero defects has not yet been hit,” Pratt said. Veeco, which is the sole supplier of EUV multilayer deposition tools, has plans to upgrade the existing Odyssey tool and launch a new platform in the 2017/2018 timeframe.

An EUV mask is considerably more complicated than conventional photomasks. The EUV mask begins with a substrate. On the back of the substrate you have some material that’s used for chucking (an electrostatic chuck is used to hold the mask to a stage in the ASML tool and in the Veeco ion beam deposition tool). On top of the substrate is a multilayer sandwich made up of 40-50 moly silicon pairs that creates a mirror. A ruthenium capping layer helps protect the mask. The top layer is an absorber, and that’s what gets patterned.

FIGURE 1 shows a small pit on the substrate. “As the multilayer gets deposited on top of it, you take what in the beginning might have been a small pit and at the top it becomes 1.5X or so larger,” Pratt said.

Where is EUV today? Billions have already been invested to build the EUV infrastructure with particular emphasis on the light source. Chipmakers have invested in ASML, and ASML acquired light-source provider Cymer. There has also been a very large Industry investment in Zeiss to build the AIMS tool, which is a defect detection and repair system at EUV wavelengths.

In July, ASML said NXE:3300 scanner imaging and overlay performance reached levels where they are engaging with customers on a strategy for the 10nm logic node insertion (23nm half pitch). Good imaging performance was shown down to 13nm half pitch, and overlay between the NXE:3300 and NXT systems, had been demonstrated at less than 3.5nm. Good performance, stability and reliability of the pre-pulse source concept was demonstrated with a rate of around 40 wafers per hour, and ASML expressed confidence in reaching the goal of 70 wafers per hour productivity in 2014.

What could derail the EUV ramp, according to Pratt, is a supply of defect-free mask blanks. “EUV is, despite many years and many dollars of investment, not yet in production. The two main gaps are the EUV light sources and the defects on the mask. As they start to make progress, people start to look more seriously at the list of things to worry about for EUV going to production. Number one on that list is the mask defects,” Pratt said. “The most dangerous (un-repairable) defects come from the ML (multilayer) coating process during mask blank manufacturing. You can’t clean them and you can’t repair them and if you have more than some very small amount, there’s really nothing you can do about it. You just have to throw that mask blank away and try again,”Pratt said.

Veeco is addressing the defect challenge in two ways. The short-term solution is an Odyssey upgrade. The longterm solution is a new platform. “The Odyssey upgrade improves the yield of the tool. But then longer term we think the next gen is needed, especially as you get out to years 4 and 5 where high volume manufacturing starts to occur,” Pratt said.