By Dr. Phil Garrou, Contributing Editor

SEMI’s second annual European 3D TSV Summit was held in Grenoble in late January. 320 attendees met to discuss the status of 2.5/3DIC and other advanced packaging technologies.

Mark Stromberg, principle analyst for Gartner, projects TSV wafer production will be > 500K 300mm equiv wafers/month or > 750MM units / yr by 2016, with a CAGR between 2013 – 2018 of 107%. By 2016 they are predicting theTSV equipment market will approach $1B.  They are also predicting that similar to the lower transistor nodes, only top tier IDM/Foundries/OSATS will participate due to the significant capex requirements.

GlobalFoundries (GF) has been detailing their imminent commercialization of 2.5/3D IC for several years. Michael Thiele, Sr. section manager for packaging reported that Rev 0.5 of their design manual and process design kit would be ready in Mach of this year with Rev 1.0 coming out in the 3Q.   The proposed GF supply chain is shown below:

Miekei Leong, VP of TSMC reported on their plans to validate high bandwidth memory (HBM) on their chip-on-wafer-on substrate ,CoWoS interposer  technology by 4Q 2014 and details on vertical stacking of memory on 28nm logic.

Eric Beyne of IMEC took a look at the cost breakdown for wafer level 3D integration for a fully loaded balanced line producing 5x 50um TSV.