BY PETE SINGER, Editor-in-Chief
It would be difficult to overstate how critical the development of a workable, high volume manufacturing EUV lithography solution is to the semiconductor industry. It is no doubt why Intel, TSMC and Samsung invested billions in ASML in 2012, and why ASML acquired Cymer in 2013.
Progress has been slower than hoped, and many are questioning if it will be ready for the 10nm generation, which is slated to go into production in late 2015/early 2016. The cover story this month looks at alternatives, including mutli e-beam and directed self-assembly.
A push to 3D devices, such as the vertical NAND, make continued scaling possible while lessening the lithography (although new challenges are created for deposition and etch technologies). The good news is that it’s possible to get to 10nm and even 7nm without EUV using multi-patterning. The only question is if it will be cost effective to do so.
Earlier this year, at the SEMI Northeast Forum held in Billerica, MA, Patrick Martin, Senior Technology Director at Applied Materials described EUV as a “huge challenge” but then noted that “beautiful, brilliant people are working on this. He said “a thousand people at Cymer spend their life trying to make this work.”
“A thousand people at Cymer spend their life trying to make this work.”
I thought this was an interesting insight. It’s too easy to only look at the myriad of technology challenges that exist in something complex as EUV and think it’s not workable. But if we consider the human factor and that so many people are dedicating their lives to make it work (not to mention the billions of dollars at stake), it suddenly seems very achievable.
One EUV proponent is our blogger Vivek Bakshi, who runs regular workshops on EUV. In August, he reported on some recent good news announced by IBM showing good results using the ASML EUV tool at the Albany Nanotech center. What was a little sad was how many negative comments were made. I suppose with something as critically important as EUV, it’s to be expected that emotions will run high. But let’s not forget those beautiful, brilliant people that are spending their days trying to make it work.
This editorial originally appeared in the September 2014 issue of Solid State Technology.
EUV is this generation’s SST. Thousands of beautiful, brilliant people spent their days trying to make the SST work. There are two problems. First, what exactly does “work” mean? The SST flew with paying passengers. Did it “work”? I think we can agree it did not. Arguably, it didn’t fail technically, but clearly it failed economically. Secondly, what is the opportunity cost of the billions of dollars and thousands upon thousands of hours of effort by these beautiful, brilliant people? What else could they have worked on? Could the billions of dollars spent pursuing x-ray lithography been deployed elsewhere? It’s cowardly to claim that this in the past, it’s “spent” money and time, and we should only focus on the future. Whether or not EUV is every deployed in wafer fabs to produce ICs, it represents a catastrophic failure, surely on the scale of the SST. If we do not learn why such beautiful and brilliant people didn’t devote a little more time to think about what they were doing, and why they were doing it, we are surely doomed to repeat it.
I agree with Diogenes.
Beautiful people are for Hollywood.
Beautiful and brilliant people worked hard on such, pardon me, scam as 157 nm litho, remember?
EUV had missed multiple entry nodes, and even if miracle does happen and it becomes real, it’ll require multiple exposures just like 197 nm optical litho does. Where’s the beef, then?
Throw in the ugly fact: EUV mask doesn’t have pellicle, but specs about 2nm or so as max particulate contamination size. Enlighten me, please, on how long mask will last in EUV stepper w/out pellicle, 1hr, 3hrs, a day, perhaps?
Intel now sees clear path to 10 and 7 nm w/out EUV. So, what’s new EUV entry point?