BY JIN YOU ZAO, STATS ChipPAC, Singapore, and JOHN THORNELL, Rudolph Technologies, Inc. Bloomington, MN, USA

The demand for 4-mask layer Cu-plated wafer-level chip scale packaging (WLCSP) is increasing rapidly, and the current capability for in-line Cu height measurements is not suitable for high volume manufacturing (HVM). Thus, metrology constrains production capacity and limits volume ramp. Furthermore, the bottleneck created by a backlog of Cu step height measurements risks the timely detection of process drift and control. For a 4-mask layer Cu-plated WLCSP, accurate Cu step height measurement is required for both the Redistribution Layer (RDL) and Under Bump Metal (UBM) to ensure consistent delivery of good electrical performance and package reliability. This is especially important as WLCSP is moving towards finer feature size and pitch to meet increasing demand for smaller form factor.

In this article, the current measurement methodology is reviewed and an alternative measurement solution is derived. Full automation capability is delivered, yet the solution is reliable and versatile enough for high-mix production volumes. For quick-turn and high-mix volume manufacturing, accurate and fast in-line monitoring is crucial for timely process drift detection and control.

WLCSP in-line process measurement challenges

Contact-based profilometers are commonly used in wafer bumping for measurement of metal feature (RDL, UBM) thicknesses due to their ease of use and their low cost of ownership. However, the method of measurement is largely semi-automatic, and the identification of exact features and measurement locations is challenging.

This becomes more acute in a high product-mix HVM environment, where measurement needs to be highly adaptive to different features on different products. As such, contact-based profilometers are limited to sampling measurements, and cannot perform 100% die inspection for process characterization.

It is thus desirable to have an automated feature measurement system capable of measuring features at precise locations on different topology on wafers in both sampling and full inspection modes.

Specifically, feature measurement for wafer bumping comprises the following configurations (FIGURE 1):

a) Cu RDL feature height measurement after Cu electro-plating, where the sputtered metal seed layer to enable Cu plating remains on the first layer polyimide surface

b) Final Cu RDL feature thickness measurement on first layer polyimide surface (PI-1) after the Cu seed layer is etched away. Accurate final Cu RDL thickness measurement would require a good gauging of the PI-1 thickness underneath, especially if the topology is not flat.

c) Cu UBM feature height measurement after Cu electroplating

d) Final Cu UBM feature thickness measurement on second layer polyimide surface (PI-2)

The development for automated feature measurement proceeded in two phases: (Phase-1) Cu step height highlight measurement on reflective metal surfaces, and (Phase-2) Cu thickness and polyimide thickness measurement on non-reflective surfaces.

Phase-1: Auto Cu height measurement

In this phase, the 3D inspection (3DI) system commonly used for solder bump height (typically greater than 20μm) measurement is explored for auto Cu feature height measurement. Typical 3DI system such as Rudolph’s WaferScanner, is equipped with the 3D triangulation laser sensor (FIGURE 2). Laser triangulation, where a laser is directed at the wafer surface at an angle of 45° and focused to a spot size of 8μm, provides fast, precise measurements of bump height and coplanarity. Through a combination of laser-scanning and wafer movement, the beam scans the entire wafer surface. A lens collects the reflected/scattered laser light and focuses it on a position sensitive detector.

To enable Cu feature height measurement (typically in the range of 2- 20μm), the Triangular laser sensor was redesigned with a spot size of 5μm, providing accuracy down to +/-0.2 μm. The laser scanning algorithm was also improved from an array to a stagger method to improve the repeatability of scanning signals. As Cu feature height measurement is influenced by the surrounding topology, the ability to select any datum for measurement is critical. This was achieved through the integration of camera-based 2D inspection to the improved triangular laser sensor system using the developed datum selection program. An automated height measurement report can be conveniently generated for further analysis through the program (FIGURE 3).

FIGURE 3. Selectable datum for Cu feature height measurement through camera-sensor integration.

To verify the consistency of measurement performance, both the improved 3D triangulation laser sensor system and contact profilometer were used to measure feature Cu height on correlation device wafers. It confirmed that the automated 3D triangulation laser sensor system registers statistically similar Cu feature height mean compared to the manual contact profilometer, but required only one-fifth of the measurement time taken by the profilometer. Wafer bumping facilities which already have an existing pool of 3DI inspection tools can be modified to extend measurement application to Cu feature height without the need for excessive new investment.

Phase-2: Auto Cu/ PI thickness measurement

While a strong signal can be derived using the 3D triangular laser signal for Cu feature height measurement after electroplating (Fig. 1, a and c), it is more difficult to establish a stable signal for Cu feature height measurement after the reflective metal seed layer is etched away, and a reference datum needs to be established on the remaining transparent polyimide surface (Fig. 1, b and c). Several conventional methods exist for non-contact measurement of step heights, such as various confocal sensors, triangulation sensors, and scanning white light interferometry. These sensors typically have difficulty differentiating between reflections from the top and bottom surfaces of a layer, that is, layer thickness. This limitation comes from the depth of focus of the objective, which in turn depends on its numerical aperture (NA). Thus, for all these techniques, sensor performance is highly dependent on objective lens.

To overcome this technical constraint, it was necessary to develop a metrology system that can measure concurrently the transparent layer thickness as well as the metal feature step height above the surface of the transparent layer. This can be achieved through the integration of reflectometry and visible light interferometry principles [3]. In this method, the direct reflection from the transparent layer provides direct thickness measurement of the transparent material, while the interferometry captures topography (distance from the sensor), allowing the system to measure the thickness of the opaque metals by scanning over the edge of the feature. This technique is called the visible thickness and shape sensor (VT-SS) system.

In the following sections we provides further description of how the VT-SS system can be adapted for feature height/thickness measurement on varying topology and opaque materials. For this work, we used the Rudolph Technologies NSX System configured with the VT-SS sensor.

VT-SS system MSA study

Measurement system analysis (MSA) seeks to qualify a measurement system for use by quantifying its accuracy, precision and stability. VLSI standard wafers with 8μm, 24μm, and 48μm step heights were used to assess gauge repeatability and reproducibility (GR&R) and accuracy of the VT-SS system, as well as system correlation on two different NSX Systems (tool matching) that were retrofitted with the VT-SS system.

A. Gauge repeatability and reproducibility
For the GR&R study, a total of ten parts on VLSI wafers (4 parts from 8μm, 3 parts from 24μm and 48μm respectively) were measured three times each, including wafer loading and unloading. FIGURE 4 shows gauge R&R for VT-SS is 1.35% of tolerance and fully meeting AIAG standard of <10%.

B. Accuracy
Step height measurement accuracy was evaluated by means of bias and linearity analysis using the VLSI step height wafers. For this study, one location on each standard wafer was measured ten times and compared to the VLSI specification for the wafer.

Based on the studies in FIGURE 5, measurement with VT-SS system shows an average bias of 0.95%, and linearity error of 0.0059%, meeting the AIAG standard of <5%.

FIGURE 5. Accuracy study on VT-SS with VLSI standard.

C. Correlation of Multiple Systems
Having established VT-SS capability, the next evaluation is system correlation on multiple tools of the same configuration. The same VLSI wafers described above were measured on a second system with the same hardware and software configuration.

A summary of results are shown in TABLE 1, and a detailed example of the 24μm step height is shown in FIGURE 6. For each wafer, the two systems produce similar results, with an offset that ranges from approximately 10nm to 30nm. Considering that the measurement uncertainty is on the order of 5nm (1-), the small system offset is within expectations.

VT-SS system application assessment

VT-SS system allows capturing of both the transparent polyimide thickness and opaque Cu feature height with a single scan from polyimide layer to Cu feature. From the part of the scan covering the polyimide, signals representing the direct measure of the polyimide thickness, the distance to the first surface of the polyimide, and the distance to a metal surface under the passivation stack are measured. The direct measure of the polyimide thickness is the measurement a standard spectroscopic reflectometer would produce. In that part of the scan where the sensor spot illuminates the Cu step height, the direct thickness peak and one of the distance peaks disappear. Only a distance peak to the surface of the Cu feature is present since the copper is opaque. The Cu step height above the first polyimide layer is then determined from the appro- priate distance measures from each part of the scan. Thus, all the desired thickness and Cu thickness measurements are reported.

To aid interpretation of measured signal peaks, a visualization program was developed for automated generation of feature thickness. FIGURE 7 shows an illustration of the program interface for visualization of measured thickness. Raw data can also be exported for further analysis.

A. VT-SS Cu RDL Layer thickness measurement
To assess VT-SS system’s measurement performance on an actual device feature, it was used to measure the Cu feature RDL thickness layer above the first polyimide (PI) layer (refer to Fig. 1, for a pictorial illustration) on a correlation device wafer. The measured RDL thickness was then cross verified with the actual measured Cu feature step height from a contact profilometer and WaferScanner

B. VT-SS Polyimide cum RDL layer Thickness
Further evaluation of the VT-SS system accuracy was achieved through comparison with cross sectional scanning electron microscopy (X-SEM) measurements. X-SEM allows evaluation of both RDL step height and PI thickness (Fig. 1, b). As discussed above the measurement sensor has the unique capability to simultaneously measure step height, i.e. a distance measurement, and film thickness. Both types of measurements must be independently evaluated for accuracy.

Conclusion

We have reported the development of VT-SS-based system on a fully automated platform for in-line process measurement of wafer bumping processes. This new metrology integrates both reflectometry and visible light interferometry principles. Based on MSA studies, VT-SS on a fully automated platform is a precise, accurate and fast metrology system. Engineering validations have shown VT-SS is highly capable in measuring critical dimensions such as RDL/UBM metal thickness, transparent polyimide/ passivation thickness, and feature sizes in one single step. It relieves the current constraints imposed by existing measurement tools on in-line process control, especially in a high mix, high volume production environment. This allows WLCSP production to move to new milestones of quality, yield, cycle time and productivity.

Acknowledgment

The authors would like to thank Harry Kam of STATSChipPAC Singapore (SCS) for his sponsorship in this project, and other team members from SCS and Rudolph Technologies, Inc. for supporting the development work.

References
1. Yole Development, WLCSP Market & Industrial Trends: 2012, Jan2012
2. Robert F. Kunesh, “Wafer Level Chip-Scale Packaging: Evolving to Meet a Growing Application Space”, Adv. Microelectronics, Jan/Feb 2013, Vol. No.1, pp14-16.
3. J. Schwider and Liang Zhou, “Dispersive Interferometric Profilometer,” Opt. Lett., Vol. 19, p. 995, 1994.

JIN YOU ZAO is with STATS ChipPAC in Singapore, and JOHN THORNELL is with Rudolph Technologies, Inc., in Bloomington, MN.