Feed-forward can be applied for controlling overlay error by using Coherent Gradient Sensing (CGS) data to reveal correlations between displacement variation and overlay variation.

BY DOUG ANBERG and DAVID M. OWEN, Ultratech, San Jose, CA

As the semiconductor industry is fast approaching 10nm design rules, there are many difficulties with process integration and device yield. Lithography process control is expected to be a major challenge requiring overlay control to a few nanometers. There are many factors that impact the overlay budget that can be broadly categorized as those arising from the reticle, the lithography tool and wafer processing. Typically, overlay budget components associated with the reticle and lithography tool can be characterized and are relatively stable. However, as published elsewhere, process-based sources of surface displacement can contribute to the lithography overlay budget, independent of the lithography process (e.g., etch, anneal, CMP). Wafer-shape measurement can be implemented to characterize process-induced displacements. The displacement information can then be used to monitor specific processes for excursions or be modeled in terms of parameters that can be fed-forward to correct the lithography process for each wafer or lot.

The implementation of displacement feed-forward for overlay control requires several components, including: a) a system capable of making comprehensive surface displacement measurements at high throughput, b) a characterization and understanding of the relationship between displacement and overlay and the corresponding displacement variability, c) a method or system to integrate the displacement information with the lithography control system. The Coherent Gradient Sensing (CGS)technique facilitates the generation of high-density displacement maps (>3 million points on 300mm wafers) such that distortions and stresses induced shot-by-shot and process-by-process can be tracked in detail. This article will demonstrate how feed forward can be applied for controlling overlay error by using CGS data to reveal correlations between displacement variation and overlay variation.

High-speed, full-wafer data collection

Historically, patterned wafer surface inspection was limited to monitoring topography variations within the die area and across the wafer with the use of point-by-point measurements with low throughput, typically limiting measurements to off-line process development. Surface inspection of patterned wafers involving transparent films (e.g. SiO2 deposited films) was typically further limited to contact techniques such as stylus profilometry.

With CGS interferometry, a high-resolution front-surface topography map of a full 300 mm patterned wafer can be obtained for product wafers with an inspection time of a few seconds. Transparent films can typically be measured successfully without opaque capping layers due to the self-referencing attribute of the CGS interferometer. Essentially, CGS technology compares the relative heights of two points on the wafer surface that are separated by a fixed distance. Physically, the change in height over a fixed distance provides slope or tilt information and the fringes in a CGS interference pattern are contours of constant slope. In order to reconstruct the shape of the surface under investigation, interference data in two orthogonal directions must be collected. The slope data derived from the interference patterns is integrated numerically to generate the surface shape or topography. In-plane surface displacements in the x- and y-directions can then be computed from the surface topography using fundamentals of plate theory (FIGURE 1).

To best utilize the capabilities of CGS technology for determining stress-induced displacement impacting critical layer overlay budgets, a “Post minus Pre” inspection strategy is typically employed, where two measurements of a wafer are taken: one prior to the process step or module of interest (the pre-process map), and a second measurement is taken on the same wafer after completing the process step or module (the post-process map). The pre-process topography map is then mathematically subtracted from the post-process topography map, providing detailed, high resolution information about the topography variation in the process step or module of interest. A series of topography maps illustrating the “Post minus Pre” process is shown in FIGURE 2.

FIGURE 2. Example of “Post minus Pre” topography CGS measurement.

The surface displacements directly impact the relative position of all points on the wafer surface, leading to potential alignment errors across the wafer at the lithography step. By measuring the evolution of process-induced stresses and displacement across multiple steps in a process flow, the overlay error due to the accumulated stress changes from those process steps can be evaluated, and the cumulative displacement can be calculated. The displacement error can then be fed forward to the lithography tool for improved overlay correction during the exposure process.

In the simplest implementation of this approach, the pre-process or reference measurement would be made following the prior lithography step, whereas the post- processing measurement would be made just before the lithography step of interest. In this manner, the total displacement induced between two lithography steps can be characterized and provided to the lithography system for overlay correction.

Stress and displacement process fingerprinting

By using CGS-based inspection to generate full-wafer topography, displacement and stress, detailed information can be provided for both off-line process monitoring (SPC), or in-line, real-time monitoring (APC) of process steps with significant process induced stress and displacement. A key consequence of the monitoring flexibility afforded by the measurement is the ability to characterize and compare within- wafer displacement and stress fingerprints of individual process chambers in a manufacturing line.

Target-based overlay metrology systems have historically been used as the only metrology tool to measure overlay error at critical lithography layers. Overlay data from the target-based overlay tools is collected after the wafer exposure step and is fed-backward to correct for the measured overlay error for subsequent wafers. As process- induced displacement errors are becoming a significant percentage of the layer-to-layer overlay budget, this post processing feed-back approach for overlay correction may not be sufficient to meet critical layer overlay specifications. Furthermore, overlay errors are often larger near the edge of the wafer where traditional overlay metrology target densities are typically low, providing only limited data for overlay correction.

The implementation of displacement feed-forward overlay correction can be
used to account for wafer-to-wafer and within-wafer distortions prior to lithography. The displacements can be characterized using an appropriate model and the model coefficients, or correctables, can be provided to the lithography tool for adjustment and control on a wafer-by-wafer basis. As shown in FIGURE 3, the CGS technique has the additional advantage of providing high-data density near the edge of the wafer (typically > 75,000 data points beyond 145 mm, sub-sampled in the Fig. 3 vector map for clarity), such that more accurate corrections can be determined where the overlay errors tend to be largest. As a result, lithography rework can be reduced and productivity increased. Case studies have revealed that a significant improvement in overlay can be achieved using this approach.

FIGURE 3. Vector displacement map showing process-induced edge distortion.

For each critical lithography step, a correlation is typically generated by comparing the traditional overlay measurement tool results to the surface displacement measured by the CGS measurement tool. Recognizing that displacement is only one component of the total overlay measurement, correlation of overlay to displacement requires effort to model or characterize the non-displacement components of the measured overlay. As a result, the appropriate correlation is derived by comparing total overlay to displacement plus the non-displacement overlay sources.

FIGURE 4 shows plots of total overlay versus displacement plus modeled non-displacement overlay sources for multiple locations on a single wafer processed in a leading-edge device flow. Figure 4a shows the x-direction data, whereas Fig. 4b shows the y-direction data. The data is presented in arbitrary units, however the same reference value in nanometers was used to normalize each set of data. The displacement data was evaluated at the same locations as the overlay target positions. For both the x-direction and y-direction data, the point-to-point correlation indicates good correlation with the correlation coefficients of 0.70 and 0.76, respec- tively. The RMS of the residuals of the linear fit to each data set are on the order of 1.5 to 2.0 nm.

FIGURE 5 similarly shows the wafer-to-wafer variation for overlay and displacement for the x-direction (Fig. 5a) and y-direction (Fig. 5b). The data in Fig. 5 are from multiple lots for the same lithography process evaluated to generate the data in Fig. 4. As with the point-to-point data, the wafer-to-wafer data shows strong correlation with correlation coefficients of 0.94 and 0.90 for the x-direction and y-direction, respectively.

The data in Figs. 4 and 5 illustrate key points regarding the correlation of overlay to displacement. First, the inherent variability of an advanced lithography process is typically on the order of 1 to 2nm. As a result, it is reasonable to conclude that the most of the scatter shown in Fig. 4 is likely associated with the variability in non-displacement sources of overlay variation. Second, the modeling or empirical characterization of non-displacement overlay sources is useful to the extent to which those non-displacement sources are constant. Consequently, if such modeling is part of the displacement feed-forward scheme in an effort to predict overlay, the model must account for known variations in the lithography process. A simple example is varia- tions in overlay performance due to differences between lithography chucks.

Displacement feed forward

It has been shown elsewhere that stress induced displacement can account for a significant fraction of the overlay error for certain critical layers at the 40nm node and below. It is therefore critical to develop the tools necessary for utilizing the measured displacement data for real-time in-line feed forward overlay correction to the scanner. One approach to this solution is to develop a system that allows the user to define the level of correction to be applied to the scanner for each lot, wafer or within-wafer zone.

FIGURE 6 shows a simplified schematic for a combined displacement feed-forward and image placement error feed-back approach. Once the process induced displacement for a specific set of process steps has been measured and correlated to overlay error, the measured displacement can be “fed forward” to the scanner in combination with traditional image placement error feedback techniques to further improve critical layer scanner overlay results. This approach is currently being implemented in leading-edge memory fabs to further reduce overlay errors on critical lithography levels and improve overall device yield.

Summary

The measurement of process-induced surface displacement can be an effective part of the overlay control strategy for critical layers at leading edge process nodes. CGS technology provides a method to comprehensively measure these displacements at any point in the process flow. Using a full-wafer interferometer, this system measures the patterned wafer surface in a few seconds and provides a map with up to 3,000,000 data points. This enables 100% in-line monitoring of individual wafers for in-situ stress and process induced surface displacement measurements. Its self-referencing interferometer allows the inspection to be made on any type of surface or films stack, and does not require a measurement target. This capability is currently being employed in numerous leading-edge memory and logic processes.

DOUG ANBERG currently serves as Ultratech’s Vice President of Advanced Lithography Applications; DAVID M. OWEN has been the Chief Technologist for Surface Inspection at Ultratech since 2006. Prior to joining Ultratech, Dr. Owen spent nearly a decade as a research scientist at the California Institute of Technology (Caltech) in Pasadena, and was the Founder and Chief Technology Officer for Oraxion Diagnostics.