By Dr. Phil Garrou, Contributing Editor
At the 12th annual 3D ASIP [Architectures for Semiconductor Interconnect and Packaging] Conference, sponsored by RTI Int, in Redwood City CA last week, Professor Mitsumasa Koyanagi of Tohoku University and Dr. Peter Ramm of Fraunhofer EMFT were the conference’s first recipients of the “3DIC Pioneer Award”.
Conference Chair Dr. Phil Garrou from Microelectronic Consultants of NC commented, “Since we are now more than a decade into the concerted effort to commercialize 2.5 and 3DIC technology it seemed appropriate to look back and document who actually led the way in this technically challenging effort. After significant study, we are convinced that the research groups in Tohoku University and Fraunhoffer – Munich were not only the first in the field, but also have continued their studies to this day to help commercialize this important leading edge technology.”
Professor Koyanagi (left) and Dr. Ramm (right) accept 3DIC Pioneering Award from conference chair Garrou.
Profesor Koyanagi’s work started back with his seminal paper “Roadblocks in achieving 3-dimensional LSI” presented at the Symposium on Future Electronic Devices in 1989. His 1995 paper “Three dimensional Integration Technology Based on a Wafer Bonding Technique Using Micro Bumps” showed a process sequence similar to todays TSV etch, thin and bond for an image sensor circuit.
Dr. Ramm began his work in the early 1990s in collaboration with Siemens under the German sponsored R&D program “Cubic Integration – VIC”. Their paper “Performance Improvement of the Memory Hierarchy of RISC-Systems by Application of 3-D Technology,” which appeared in IEEE Trans on Components, Packaging and Manufacturing Technology in 1996 woke up the larger community to the possibilities of using 3DIC. A key patent from that era was USP 5,563,084 “Method of Making a 3 Dimensional Integrated Circuits” which issued in 1996.