Recent breakthroughs in materials engineering of low-resistance W barriers/liners and bulk fill are making it possible to extend W use to next-generation devices.
BY JONATHAN BAKKE, Applied Materials, Santa Clara, CA
Tungsten (W), with its low resistivity and minimal electro-migration, has long been used for a variety of applications in fabricating semiconductor devices. For instance, it is used for logic contact, local interconnect (LIC), and metal gate (MG) fill as well as DRAM buried word line and contact and 3D NAND MG and contact. Sustained scaling, however, is posing challenges to its continued use with conventional process flows. Interconnect dimensions have shrunk to the point at which contact resistance is becoming an obstacle to realizing optimum transistor performance; fill integrity degrades as aspect ratios and the degree of re-entrance increase, making it difficult to ensure high-quality metallization.
At earlier nodes, larger dimensions made W fill possible using conformal CVD deposition. Now, overhang around the tops of ultra-small openings or bowing from the interconnect etch open preclude the conformal process from completely filling features without voids, while center seams are an inevitable result of conformal deposition, even in the absence of voids. These attributes render extremely small features vulnerable to breach during CMP, causing high resistance or complete failure of an inter- connect. High feature densities and lack of via redundancy in advanced chip designs mean that a single void can cause complete device failure and significant yield loss.
Fortunately, recent breakthroughs in materials engineering of low-resistance W barriers/liners and bulk fill are overcoming these limitations and making it possible to extend W use to next-generation devices. The former lower resistance by simplifying fill film requirements and enlarging the volume available for W fill; the latter eliminates undesirable seams to create more robust structures.
Low-resistance liners
To date, high-resistivity TiN has been predominantly used as an adhesion layer for CVD W and to block fluorine penetration during the bulk fill process. W does not grow directly on TiN; thus, it requires deposition of a nucleation layer before the fill step. As logic devices scale through the 10 nm node and beyond, the maximum critical dimension (CD) of the LIC willbe
Metal-organic deposition of thin W-based films offers an ideal solution, because it can eliminate high-resistance liners and nucle- ation layers while maintaining adhesion and fluorine-barrier properties equiv- alent to those of the current process flow. A new W liner has been developed that lowers line resistance for further device scaling: plasma-enhanced (PE) CVD W that nucleates on metal and oxides.
The PECVD W film is produced using a specialized chemical in the presence of reactive plasma that breaks down the ligands. The film composition is primarily W, and the atoms from the decomposed ligands are bonded to the W. The amorphous character of the film and the dopants in it from the ligand lead to good adhesion to dielec- trics and fluorine barrier properties in the 20-30Å range.
FIGURE 1 shows a simulation of a contact plug in the 4-30nm range. The model contains parallel and series resistors for the plug and through resistance. Features are assumed to be straight wall trenches. Resistance of 12 μΩ*cm is used for W at all thicknesses, which under-estimates the benefit of PECVD W. Scattering at film interfaces is not taken into account. The inflections in the curves (from right to left) occur when a film is removed due to volume constraints. It is clear that the benefit of PECVD W increases exponentially as CDs decrease, especially without the nucleation layer.
FIGURE 1. Plug resistance simulation demonstrates the significant benefit of PECVD W without a nucleation layer.
SiO2 trench structures with CDs ranging from 10nm to 150nm and a depth of 100nm were used to investigate W line resistance and evaluate gap-fill performance. As shown in FIGURE 2, line resistance in a ~10 nm CD dropped by nearly 90% compared with the conventional stack.
FIGURE 2. PECVD W plus gap fill reduces line resistance by nearly 90% over the conventional stack. The inset TEM shows conformal gap fill and CMP integration for PECVD W.
Seam-suppressed gap fill
Until now, feature dimensions have made W fill integration possible using nucleation followed by conformal CVD deposition – which always leaves a seam in features. At CDs
A new approach employs a unique, “selective” suppression mechanism that results in a bottom-up fill free of seams or voids. Pre-treating the nucleation layer creates preferred W growth from the bottom of the structure upwards and less on the field, minimizing the likelihood of void-creating pinch-off and seams (FIGURE 3). Experiments showed the process to be successful on structures with CDs ranging from 10nm to 150nm.
FIGURE 3. a.Cross-sectional TEM image of SSW partial fill of 30nm CD,100nm deep trench pattern with overhang created byAr sputter and PVD Ti. (b) TEM image of seamless SSW fill of the same structure. (c) TEM image of standard CVD W gap fill with seam.
Electrical tests confirmed that SSW lowered line resistance compared to that of conventional CVD W (FIGURE 4). Post-CMP defect analysis by top-down view SEM revealed a narrow seam in conventional CVD W after W CMP (FIGURE 5a), while none is visible after SSW fill (FIGURE 5b).
FIGURE 4. Line resistance comparison of SSW and conventional CVD W on 10nm trench.
FIGURE 5. Top-down SEM image of a) conventional CVD W process with visible seam in the center of the trench and b) SSW fill on the same structure.
Conclusion
For the next several nodes of logic and memory fabrication, W will remain an important material in interconnect and gate metallization. However, as scaling continues, transi- tions in process flows will be necessary to achieve low contact and line resistance while maintaining gap-fill integrity. A new W-based barrier/liner has been produced through precision materials engineering that improves device performance and integration while simplifying process flows. Similarly, a new SSW gap-fill process increases the volume of W (potentially lowering resistance), creates more robust features for post-fill integration, and relaxes requirements on CMP and dielectric etch steps, thus delivering performance, device design, and yield benefits.
For further detail on the processes presented in this article, see Bakke, J., et al., “Fluorine-Free Tungsten Films as Low Resistance liners for Tungsten Fill Applications” and Kai,W.,etal.,“ImprovingTungstenGap-FillforAdvance Contact Metallization,” presented at the 2016 IEEE Inter- national Interconnect Technology Conference.