A*STAR’s Institute of Microelectronics (IME) has established a development line to accelerate the development of fan-out wafer level packaging (FOWLP) capabilities for next-generation Internet of Things (IoT) technologies. The FOWLP development line, which is built upon existing infrastructure at IME’s facilities at Singapore Science Park II, and its new facilities at Fusionopolis Two, will allow IME and its partners (see Annex A for list of partners) to develop technologies that serve a wide range of markets such as that of consumer electronics, healthcare and automotive.
The IoT is set to become the next growth driver for the semiconductor industry, as demand for internet-connected devices continues to soar. FOWLP is an emerging breakthrough chip packaging technology platform aimed at meeting the technology requirements of next-generation electronic devices that require ultra- low power consumption rates, smaller package profiles, higher performance; and all made at a lower cost.
IME’s FOWLP development line is equipped with fully automated tools that can perform the “mold-first” and “Re-Distribution Layer (RDL)-first” method in multi- chip fabrication. The “RDL-first” method is expected to achieve a higher reliability rate compared to the conventional “mold-first” method traditionally used by the semiconductor industry. IME and its partners will jointly develop tools and processes for next-generation FOWLP technologies such as high speed Copper (Cu) pillar plating, Physical Vapor Deposition (PVD) process to control the wafer warpage, moldable underfilling for Chip-to-Wafer, as well as over molding on wafer with vertical Cu pillar/Cu wire interconnections using wafer level compression molding, plasma descum of small vias and warpage adjustment, etc.
To unlock the potential of FOWLP and accelerate the development and adoption of these innovative process technologies by the industry, IME has also formed a consortium comprising leading OSATs, Materials, Equipment, EDA, Fabless partners (see Annex A for list of consortium members).
The FOWLP development line consortium will allow members across the value chain to co-share resources on an open innovation platform, and draw upon IME’s rich portfolio of advanced packaging capabilities to address the complexities in system scaling and heterogeneous system integration. The FOWLP development line will be a test-bedding platform through which consortium members could gain new insights on requirements of FOWLP by testing and developing new processes, paving the way for high-volume manufacturing.
The FOWLP development line utilises tools already in use in major OSATs, and will allow processes, materials and integration flows developed at IME to be smoothly transferred. Through this development line, fabless companies could also make quicker decisions on package structure, integration flows, processes, materials and equipment for their new products; so materials and equipment suppliers could expedite the development of their products and increase their adoption.
“The launch of IME’s FOWLP development line and consortium will enable us to advance pre-competitive R&D that positions the semiconductor industry for growth opportunities in the thriving IoT market. Through an open and collaborative approach, the consortium will drive the development and the transfer of innovative technologies from pilot-scale to commercial production more easily and quickly,” said Dr. Tan Yong Tsong, Executive Director, IME.
“We are extremely proud to be a part of IME’s FOWLP consortium and play an active role in this great initiative. This broad industry cooperation will help solve one of the largest challenges faced by the semiconductor industry in the area of achieving higher density in advanced packaging. ERS is committed to developing new thermo-management solutions to enable next generation of FOWLP technologies,” said Mr. Klemens Reitinger, Chief Executive Officer, ERS Electronic GmbH.
“We are pleased to be collaborating with IME in this FOWLP development line consortium (DLC). We have benefitted from the experience in the previous consortium on High Density FOWLP, and are confident that with our combined experience and knowledge, the consortium will accelerate the development of FOWLP and establish an innovative cost-effective manufacturing process to further the mass adoption of FOWLP,” said Mr. Tong Liang Cheam, Vice President of Corporate Strategy, Kulicke & Soffa.
“It’s exciting to participate in this new FOWLP development line at IME to advance chip packaging. Nordson has a successful history of working on innovations in the semiconductor packaging industry, and this consortium is positioned well to produce excellent solutions,” said Mr. Joseph Stockunas, Vice President, Advanced Technology – Electronics Systems, Nordson Corporation.
“It is through collaborative efforts, such as that of the FOWLP development line and consortium that the semiconductor ecosystem can advance. Our engagement with the consortium will not only benefit our customers, but the industry as a whole in driving the adoption of this technology for emerging High Bandwidth Memory (HBM) and diverse IoT applications,” said Mr. Asim Salim, Vice President of Manufacturing Operations, Open-Silicon. “Through Open- Silicon’s extensive experience in 2.5D ASIC design, and the expertise of the consortium, issues like cost will be mitigated, thus enabling OEMs of all sizes to adopt FOWLP technology.”
“We are delighted to be a part of IME’s FOWLP development line consortium and continue to play an active role in this open innovation initiative. Industry-wide cooperation is key in overcoming the many challenges faced today by the electronics packaging industry. Orbotech is committed to developing new cost- efficient solutions to enable the next generation of advanced packaging technologies, which in turn will impact the industry’s next inflection point,” said Dr. Abraham Gross, Chief Technology Officer and Head of Innovation, Orbotech.
“As demand for high speed, high bandwidth data connectivity in consumer electronics continues to grow, the performance and cost challenges limiting the implementation of high frequency millimeter wave applications have the potential to be addressed with FOWLP solutions. We look forward to working with the FOWLP development line consortium to realise the benefits of FOWLP technology for mmWave antennae devices in emerging markets such as automotive and the Internet of Things (IoT),” said Mr. Shim Il Kwon, Chief Technology Officer, STATS ChipPAC.
The Institute of Microelectronics (IME) is a research institute of the Science and Engineering Research Council of the Agency for Science, Technology and Research (A*STAR).
What IME is calling a FO WLP is in fact a good old Flip Chip using micro pillar Cu bumps Flip chip bonded to a thin coreless substrate containing the RDL, underfilled per standard flip chip assembly process then the whole assembly molded. Nothing new there except for the rebranding of Flip Chip as the more trendy FO WLP. What IME is also claiming here is that their full Flip Chip based flow is more reliable than the standard bump / assembly less FO WLP flow used by TSMC for Apple. Them be fightin words !