3-D stacked wafer-level packaging
03/01/2000
3-D stacked wafer-level packaging
New through-silicon methodology offers flexibility.
SERGEY SAVASTIOUK, Ph.D.
OLEG SINIAGUINE, Ph.D.
ED KORCZYNSKI
As electronics applications shrink in size, integrated circuit (IC) packaged devices must be reduced both in footprint and in thickness. The main motivation for the development of smaller packages is the demand for portable communications devices, such as memory cards, smart cards, cellular telephones, and portable computing and gaming devices. End-users of such electronic devices are interested in greater functionality per unit volume, not relatively simplistic metrics, such as transistors per chip or circuit speed.
With many anticipated challenges in continuing to reduce individual chip area (i.e., the X and Y dimensions), greater functionality per volume can be achieved by reducing the overall package height (the Z dimension). With other components of the final package already thinned as much as possible, further reductions in package thickness will require thinning of the die itself.
Early through-hole package types, such as dual-in-line packages (DIPs), had package thickness dimensions of 150 mils (4 mm). With the migration to smaller footprint surface mount components, such as small-outline integrated circuits (SOICs), the package thickness dimension was reduced to the 50 to 90 mils (1.2-2.5 mm) range. Package thickness was then driven down to about 20 mils (0.5 mm) for applications like smart card modules and miniature ball grid arrays (BGAs). As this thinning trend continues, today`s chip scale package (CSP) thickness specifications approach 10 mils (0.25 mm).
In the early generation of through-hole packages, such as DIPs, chips from 4- to 6-in. diameter wafers were typically 21 mils thick so that very little wafer thinning was required. More recently, surface mount devices require die thickness of 10 to 12 mils and are mostly processed on 6-in. (150 mm) and 8-in. (200 mm) diameter wafers.
Demands for wafer thinning will be even greater with the inevitable move to 12-in. (300 mm) diameter wafers. Larger wafer diameters require thicker silicon to withstand wafer manufacturing, while packaging trends continue to require thinner final chips for the next generation of components (Figure 1).
Figure 1 demonstrates that the industry has decreased chip thickness by about 5 percent each year since wafer thinning became a requirement. This trend is expected to continue and, by doing so, it will enable the industry to continue doubling component density (expressed on a unit volume basis) every 18 to 24 months.
Thin Die Functionality
In addition to volume advantages, there are important performance benefits to reducing the thickness of silicon die; such benefits can be categorized as both device performance and reliability enhancements.
Thermal Resistance: Thinning the die reduces the serial thermal resistance between the active circuitry and the backside of the chip which can be in contact with a heat sink. Thermal resistance is a critical parameter for a variety of chips, such as power and high-speed microprocessors. The thermal resistance of a solid material can be defined by the equation
Q = t/(k*A)
where Q is the conductive thermal resistance (°C/W), t is the thickness or distance through which heat must travel (m), k is the thermal conductivity (W/[m*K]), and A is the cross- sectional heat flow area (m2).
The thermal resistance of a silicon die of area 10 x 10 mm and thermal conductivity of 145 W/m*K is 0.025°C/W for 14-mil thickness, and is reduced to 0.0035°C/W for a 2-mil thickness. If a die attach material - such as 8020 gold/tin - with a thermal conductivity of 57 W/m*K and thickness of 1 mil is used, then the combined thermal resistance is reduced correspondingly from 0.03°C /W to 0.008°C /W.
Device Reliability: Thin die minimize the stress on the device circuitry because of mismatches between the coefficients of thermal expansion (CTE) of materials within the packaged device (Figure 2). This is particularly the case in die cracking problems exhibited in power devices.
With a CTE of silicon of approximately 4 x 10-6/°C and a CTE of a copper alloy lead-frame material of 16 x 10-6/°C, a significant amount of bond stress will be induced by thermal cycling. Reducing the die thickness dramatically reduces stress in the die and allows it to flex with the board; thus, the chance of both ball bond and silicon fracture is reduced.
Device Electrical Performance: Mechanical thinning processes - such as backgrinding - distort the silicon crystal lattice as material is scraped away. This inherent residual damage produces stress fields that can degrade device performance.
Damage to the silicon lattice as a result of severe stress can produce noise in certain device types, such as precision power amplifiers. In similar device types, such as op amps, inconsistent or high stress fields can adversely affect off-set voltage and current performance and, thereby, reduce yield and downgrade parts.
Stacks: Die must be thinned to be used in vertical memory stacks. It is desirable to fit chip stacks inside standard packages, and this requires thin die. Chip-stack designs are also attractive for the combination of logic/memory, optical/ electrical, analog/digital ("mixed-signal") and microelectromechanical systems (MEMS) functionalities.
Wafer Thinning Options
Four different methods can be used to reduce wafer thickness: mechanical grinding, chemical-mechanical polishing (CMP), wet etching and atmospheric downstream plasma (ADP) dry chemical etching (DCE), which is a new technology.
While mechanical surface grinding is the most commonly used process to thin wafers after processing, it can induce significant stress and damage the silicon wafer. Grinding can reduce bulk wafer thickness at a significant rate, thereby making it a very affordable process. Today, backside grinders are installed both in the wafer fab and in some assembly areas.
CMP has been investigated as an extension of backgrinding. By reducing the mechanical force and adding chemicals to the slurry, some residual damage can be reduced. However, both process complexity and reduced removal rate can result in a relatively slow and expensive process.
Wet etching can reduce some post-grinding residual damage, provided that wafers remain relatively thick to withstand physical handling. Process control difficulties typically limit wet-etch processes, so they cannot effect significant wafer thinning.
ADP-DCE has the thinning capabilities of grinding with the stress removal capabilities of wet etching. The all-dry ADP source (Figure 3) can produce a chemical isotropic etch that removes residual backside silicon damage, and allows for simple thinning to 2 mils and below.
While DCE has a significantly higher silicon removal rate as compared to wet etching, it does not offer the same throughput as grinding. However, the combined benefits of DCE`s stress removal and wafer thinning create a technology shift.
The benefits of reducing residual stress in processed wafers are immense and far-reaching. Some advantages include:
• damage- (stress-) free crystal lattice enhances device operating frequencies and decreases the noise within the device,
• uniform stress fields maintain matched characteristics of embedded devices,
• thin, stress-free die provide a lower VCE(sat) in discrete devices, and
• improved backside morphology improves thermal and electrical characteristics of the device.
Customer process demonstrations show that DCE can reduce 8-in. wafers down to 2-mil thickness while maintaining a total thickness variation (TTV) of 2 percent or less.
The ADP-DCE process is contact-less and does not require that protective tape be applied to the wafer topside, which reduces processing costs and allows for the ability to process bumped wafers.
3D WLP Concepts
Wafer-level packaging (WLP) holds great promise for the semiconductor manufacturing industry to reduce packaging costs and cycle-times. However, new cost-effective process technologies are needed before this can be fully realized. Many organizations are actively developing such WLP process technologies.
Perhaps the best outcome from WLP is the stacking of wafers to form 3D multi-chip packages (MCPs). 3D WLP can provide many advantages over both horizontal MCPs and single system-on-chip (SOC) designs: cost, performance, time-to-market and product lifecycle management. For instance, horizontal MCPs must be fabricated on the chip-scale, so WLP economies of scale do not apply, and they are speed constrained by the long horizontal leads between chips. SOCs require greater costs in design and manufacturing, because multiple divergent functionalities are difficult to integrate together in the same silicon, and they can be performance constrained when mixed functionalities are integrated (for example, digital noise can degrade analog function in mixed-signal chips).
SOCs can also be slower to design than MCPs, because more on-chip functional integration requires more design integration and time. SOCs must also be redesigned when any portion of functionality must be changed. MCPs usually allow for effective re-use of most of a system design by only having to redo one section.
Through-silicon Interconnections
A major technical obstacle to mass-produce 3D WLP is forming die interconnections within a vertical stack. Lacking a cost-effective technique to form interconnections through a silicon wafer (from the front- to the back-side), a manufacturer currently has to link them over the die edges. Unfortunately, over-edge interconnections can be more art than science and are barely automated, thus they can be unreliable and expensive.
A new through-silicon manufacturing technology - based on ADP-DCE methods - allows for the interconnection of two or more wafers in a vertical stack. These interconnections are formed at the wafer-level, and allow for 3D wafer-level packaging.
Through-silicon interconnections are formed in two major sequences. The first sequence forms deep metal vias on the front side of a wafer (Figure 4, steps A-D), using standard high-volume manufacturing processes. After these vias are connected to top-side circuitry, an isotropic ADP dry-chemical etch of the bulk silicon from the backside (without a mask) occurs so the deep through-silicon vias are exposed on the backside (Figure 4, steps E-H).
Forming and maintaining the electrical isolation layer between the through-silicon via-metal and the silicon substrate is critical to the success of the manufacturing process-flow. The plasma enhanced chemical vapor disposition process to initially form the isolation layer is simple and has shown long-term success in volume IC manufacturing. During DCE backside etching, the bulk silicon etches approximately ten times faster than the oxide isolation layer. The bottom oxide is cleared when the silicon etch reaches the bottom of the vias, but the oxide remains on the via sides. Consequently, as silicon continues to be removed from around the vias, the side oxide is "peeled" back at a slower rate; it is impossible to over-etch and lose the isolation. The natural etch selectivity of DCE results in a good manufacturing process to form electrically isolated through-silicon interconnections (Figure 5).
If wafers are properly prepared with embedded through-silicon vias during frontside processing, then the ADP-DCE process can potentially provide thinner wafers and backside contacts in a single step. To minimize manufacturing costs, only a single mask (the topside mask for via etch, step A in Figure 4) is required to form the final via structure, while all other via-formation steps (B, C, D, G and H) can be self-aligned.
Once through-silicon vias can be formed, then a variety of single-layer and stacked WLPs can be manufactured in high-volume. The simplest implementation is a single-layer WLP. With the area-array contacts on the wafer backside, testing can be easily performed on topside contact pads that remain right-side-up after bonding to substrates.
Stacked 3D WLP can be performed in a variety of ways to produce a wide variety of final packaged devices (Figure 6). The simplest 3D WLP incorporates a standard flip-chip wafer that is bonded upside-down to a bottom silicon wafer prepared with through-silicon vias; this approach allows for the top chip to remain the same (no redesign), while the bottom chip can incorporate the vias with integrated passive components and/or divergent active device functionality. If redesigned with through-silicon vias, however, the top flip-chip in a two-chip stack could evolve into one of the middle chips within a higher stack.
Conclusions
Thin die enable thinner packages, often with improved device performance characteristics. ADP-DCE allows for the thinning of wafers to 2 mils without residual damage to the backside silicon or topside circuitry. Wafers that are fabricated with embedded topside through-silicon vias can be ADP-DCE thinned to expose backside via contacts with self-aligned electrical isolation. Once backside contacts can be cost-effectively fabricated, then a variety of affordable wafer-level packaging process flows can be run in high-volume manufacturing.
SERGEY SAVASTIOUK, co-founder and CEO, OLEG SINIAGUINE, co-founder and chief technical officer, and ED KORCZYNSKI, director of marketing, can be contacted at Tru-Si Technologies, 657 N. Pastoria Ave., Sunnyvale, CA 94086; 408-720-3333; Fax: 408-720-3334; E-mail: [email protected], [email protected] and [email protected].
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Figure 1. Wafer thickness for processing increases with diameter, while the final chip thickness from the wafer decreases.
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Figure 2. Thin chips flex to relieve ball-bond stress induced by CTE mismatch, for increased reliability.
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Upper left, Figure 3. Photo of the atmospheric downstream plasma (ADP) source being used to activate CF4 gas into reactive, neutral, mono-atomic F gas for silicon etching.
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Figure 4. Beginning of through-silicon process: (a) deep etching of via structures, (b) PECVD oxide inside via, (c) PVD metal over oxide, (d) via fill. Completion of through-silicon process-flow: (e) topside passivation, (f) topside connection to multilevel metal, (g) ADP-DCE selective backside thinning exposes backside contacts, (h) optional backside passivation.
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Figure 5. SEM of a backside bump array produces by the through-silicon process (Figure 4). The final wafer thickness is 70 microns, and the bumps protrude 30 microns below the surface.
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Figure 6. An active wafer is joined to a passive interposer or other active wafer using any inconvenient bonding technique; the top wafer is then thinned by ADP etching to expose through-silicon contacts. Additional wafers can be added.