The back-end process: Step 12 - Packing and shipping Material integrity issues
12/01/2001
BY RALPH HENDERER AND LYNN MILBRETT
 Figure 1. Shippers designed to transport finished wafers. |
The supplies used to protect and transport critical materials in the semiconductor industry are becoming more consequential in the current business and technical environment. To succeed in this changing marketplace, it becomes important to evaluate each process in the semiconductor manufacturing flow to locate opportunities to cut costs and increase productivity without sacrificing product quality. One area to explore this methodology is in the packing and shipping process.
Packing and shipping finished wafers, singulated bare die and packaged integrated circuits (ICs) is a critical process step in the semiconductor industry, and one that substantially impacts productivity and profit margin to those in both the front end and back end of the market. However, every manufacturer performs this function differently based on its core business operations, geography and the product it manufactures. Despite these differences, there are some basic issues to consider in the packing and shipping process, including integrity challenges in relation to physical, chemical and electrical damage to wafers, chips, and packaged devices; environmental issues and concerns; and how a manufacturer's approach to these challenges can affect the bottom line. This article will identify key areas that should be considered when choosing a packing and shipping approach.
Packing and Shipping Methods
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Methods for packing and shipping include:
horizontal wafer shippers designed to transport finished wafers (Figure 1); bare die trays to support bare die and chip scale package (CSP) component processing and delivery (Figure 2); Joint Electronic Device Engineering Council (JEDEC) trays for packaged IC processing and shipping (Figure 3); and tape and reel for IC shipping and handling.
 Table 1. Representative comparison of the jig tray approach compared to JEDEC trays. |
Before examining technical challenges, there are strategic decisions to consider. Packing media, like trays and carrier tape, encompass a variety of applications, and this proliferation can be costly and inefficient. Manufacturers and suppliers can help reduce this proliferation through participation in a standards process. By limiting the number of variations in each packaging media type, a semiconductor manufacturer can identify significant savings in the amount of time and money traditionally required to develop custom media. This is one reason why the industry continues to work through standards organizations, such as JEDEC. The move toward tightening these standards will make packaging media easier to adapt to a number of different companies, thereby preventing the suppliers from manufacturing many variations of the same packaging type. The result is a lower product cost and a faster turn-around time to deliver the product.
Material Integrity
Material integrity issues play a large role in the packing and shipping process, and if not addressed properly, can often result in decreased fab and assembly productivity, reduced throughput and yield loss. These integrity challenges break down into physical, chemical and electrical problems and run across all shipping methods for wafers, chips, and packaged devices.
Physical integrity challenges include damage to wafers, bare die or packaged chips that can be seen by the human eye (such as cracks or chips) and problems that can not be seen, like corrosion, stress and opened/shorted circuits. As electronic components in the semiconductor industry become smaller and more complex, so does the means of packing and shipping. Packaging media must be able to hold the wafers and ICs so that they are retained in the same spot, and rotation and movement must be diminished in the handling process. Moreover, wafers and ICs that do not fit well in packaging media will not be protected in the shipping process. Again, the results are a lower yield at a point in the process that may not even be noticeable to upstream manufacturing entities, such as IC fabs. However, a safe and secure shipping and handling product does not necessarily have to be custom made. An example of this is the jig tray approach, which can be just as effective and reduce tooling cost and shorten leadtime (Table 1). A jig tray is a tray that fits inside a JEDEC tray and is designed to protect and transport smaller forms of media.
Chemical damage is a growing concern and an integrity challenge that needs to be understood and managed. Chemical damage consists of outgassing and organic and inorganic contaminants that come in contact with wafers, chips, or packaged ICs. The packaging media must be properly designed to protect the integrity of the material being shipped, and it needs to be appropriate for the environment. If moisture is present in the shipping process and the packaging media is not designed to combat moisture, it could act as a vehicle for contaminants to travel to susceptible areas of the product. This could corrode and degrade the wafer or IC.
Material Characteristics
 Figure 2. Bare die trays to support bare die and chip scale package (CSP) component processing and delivery. |
It is also vital to understand the performance capabilities and cost associated with the materials involved in packing and shipping - as well as the logistical process - to prevent problems that could impact the integrity of the products. The quality of polymer used to create packing and shipping material is very important, and one that is sometimes overlooked when considering costs. The polymer price should be evaluated over the entire semiconductor process flow and over the life span of the packaging media to understand the full impact (Table 2). A polymer that is more expensive may provide cost savings in several areas of the process flow. It is also important to know the outgassing characteristics of a polymer to understand how they affect the performance of internal and external packaging and the precautions that can be taken to assure safety.
Another area not to be overlooked is the role that outdated technology can play. Many manufacturers continue to use older packing and shipping products created from sub-standard materials that can affect the shipping media's dimensional stability and contamination levels. Using older packaging media created with outdated technology can result in wafer scratching, breakage and increased tool calibration time.
Electrical Issues
Electrical issues can also affect the integrity of wafers, chips or packaged ICs. These problems involve currents that are in close contact to a wafer or die because of effects like static discharge. Many in the industry are unaware of this challenge because the problem can be hidden by multiple yield issues. Most natural-state commercial plastics (polymers) are electrical insulators, and an electrical charge deposited on this surface is long-lived; the longer the lifetime of the charge, the more likely it is to cause damage to electronics that come near or into contact with it. There have been a number of methods to make these polymers either static dissipative or electrically conductive. These methods are chemical additives, conductive fillers, and inherently dissipative and conductive polymers. Depending on the method used, it could affect the performance of the final product and again expose it to chemical damage.
Testing and Environmental Issues
 Figure 3. Trays for packaged IC processing and shipping. |
The process, materials and environment used to pack and transport wafers and ICs are responsible for many integrity issues. However, testing and research can substantially reduce risk and increase the safety of this process. The International Safe Transit Association has test procedures that simulate a product shipment (via land, water or air) to determine that the shipping containers protect the product and transport it safely. There are also tests available to evaluate materials that come in contact with the final product; the test can be used to ensure a decrease in chemical damage. The key in preventing integrity issues is by maintaining control in the materials used to create packaging media and to use packaging media that has been specifically designed to protect the integrity of finished wafers, singulated bare die and packaged devices.
Environmental processes in packing and shipping can also contribute to a manufacturer's bottom line. Recycling and disposing of packing/shipping materials can be costly and time consuming. There are new environmental restrictions that make it increasingly difficult for manufacturers to handle the task on their own. Outsourcing is one option to consider, and an area where the industry should continue to push back on suppliers to help find solutions. Properly designed packaging media is another area that is essential in eliminating excess packing/shipping materials, and will reduce costs in shipping materials and freight associated with optimizing space during shipments and disposal.
Conclusion
Integrity challenges and environmental issues have an enormous impact on the packing and shipping process. The way in which they are resolved greatly affects productivity and profits. By understanding the material challenges involved in the packing and shipping process, and the options available to combat those challenges, manufacturers are empowered with tools to help them make the best decision for their business. AP
Ralph Henderer, marketing director of test, assembly and packaging systems, and Lynn Milbrett, engineering manager of test, assembly and packaging systems, can be contacted at Entegris, 3500 Lyman Blvd., Chaska, MN 55318; 952-556-3131; Fax: 952-556-1880; E-mail: [email protected] and [email protected].