Is wafer-level packaging ready for 300 mm?
07/01/2001
SECAP is making progress on the many challenges
BY MICHAEL TöPPER, HERBERT REICHL, PAUL SIBLERUD, GARY SOLOMON, HANS AUER, JIM QUINN, DIETRICH TöNNIES AND ELMAR CULLMANN
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Packaging has moved from simple "housing" to a technology that has to satisfy the ever-increasing needs for higher electrical performance, further miniaturization, the highest reliability, and thermal and power management, at steadily decreasing costs in microelectronic systems. Wafer-level packaging (WLP) has shown to be a promising solution in a number of applications. This technology will further benefit from the industry's transition to 300-mm technology.
With wafer-level techniques, cost per package is primarily determined by the number of die per wafer rather than the number of I/Os per device. Therefore, larger wafer sizes and higher I/O counts make wafer-level packaging very cost effective compared to conventional packaging technologies based on wire bonding or interposers. Today, wafer bumping and wafer-level packaging technologies are relatively mature on 200-mm or smaller wafers. The Semiconductor Equipment Consortium for Advanced Packaging (SECAP) is making progress in providing a cost-effective approach to 300-mm advanced packaging. Figure 1 shows a 300-mm silicon wafer with processing for wafer-level packaging.
What is Wafer-level Packaging?
System integration and packaging affect the functionality, quality and economy of microelectronic products. Because of this, advanced packaging technologies are no longer the niche technologies they used to be. Packaging moved from a simple IC housing that protects the silicon structures from the outside world to one of the most critical enabling technologies for future IC generations.
Packaging design tradeoffs can no longer be made independent of the chip, board, assembly process, environmental aspects and the whole microelectronic system. In the past couple of years, WLP has emerged as a new basic packaging concept. WLP in general includes wafer bumping technologies, as these are also wafer-level processes, as well as the WLP technology, where the die and package are manufactured and tested on the wafer, then singulated by dicing for the assembly in a flip chip fashion. All WLP technologies are true chip size rather than chip scale packaging, because the package is completed at the wafer level.
Chip scale package (CSP) refers to approaches where the package is smaller than 1.2 times the die size (x-y area). Wafer-level CSPs are true chip size packages that are manufactured and tested on the wafer prior to dicing. A feature of the wafer-level approach for CSPs is that there is no bonding technique inside the package.
Flip chip in package (FCIP) refers to approaches in which the chips are mounted on chip carriers before final surface mount attachment. This is often done with high I/O ICs like microprocessors and ASICs, and that approach is not a true WL-CSP. Bumping of the dice for FCIP, however, is usually performed in a wafer-level technology, and therefore the bumping of these wafers is included into WLP.
Bumping of 300-mm Wafers
In recent years, several wafer bumping technologies have been established. Figures 2a and 2b show the split among different technologies. These charts include not only flip chip die, but also gold bumping for TAB and wafer-level CSPs. The most common technologies are electroplated gold bumping (mainly LCD drivers), electroplated solder bumping, C4 evaporation and photo stencil processes. Looking five years ahead, it is expected that the number of bumped wafers will increase by a factor of six. All of the above technologies, except the traditional C4 evaporation process, are expected to increase considerably in the next few years. Not all of them will be important for 300 mm, however. The C4 process, for example, with its molybdenum mask, is too expensive to be an option for 300 mm. On the other hand, ultra-fine pitch gold bumping for LCD drivers is just now undergoing the transition from 150- to 200-mm wafers. Therefore, the main focus for 300 mm will be on solder bumping and wafer-level redistribution technology.
 Table 1. Projections for range of number of I/Os per package for various product sectors, as defined by ITRS. |
A seamless process flow of the goal of WLP, and specific challenges for WLP technologies include thick resists and uniform electroplating. The different equipment used in WLP can be used to make sure that each process step is optimized for the requirements of the subsequent steps. This is why some companies operating in this arena joined forces (as SECAP) to address the interoperability of their equipment for the benefit of the complete manufacturing line. Synergy among the sputtering, photolithography and electroplating processes is important for a high yield process on 300-mm wafers.
A number of equipment and material challenges had to be addressed to introduce a 300-mm technology. One was the availability of precision 14-inch photomasks for full-field exposure of 300-mm wafers. Full-field patterning provides the flexibility needed to place arbitrary patterns, different from the step-and-repeat field layout, at the wafer periphery. Exposure with sufficient intensity, uniformity and CD-control within the same specifications as for 200 mm had to be achieved. The same was true for the sputtered under bump metallization (UBM) layers and the plating heights on a 300-mm wafer if electroplating was to be applied (specifically for high pitch applications). SECAP has demonstrated that there are no basic barriers for the industry's move to 300 mm. The first bumped wafers based on an electroplating process with bump sizes down to 20 µm were presented in April 2001.
What is Driving WLP on 300 mm?
Six 300-mm fabs are scheduled to start production in 2001, and 14 are expected to open in 2002. The demand for 300-mm wafers in the next five years will increase from 1 percent of all wafers to more than 17 percent in 2005, according to Dataquest. The industry's transition to 300-mm technology has focused heavily on front-end equipment and automation issues, but back-end equipment also needs to be part of this transition because of WLP.
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Advanced packaging technologies for 300 mm are usually developed for high-volume devices like DRAMs. However, microprocessors, SRAMs and ASICs will follow this trend shortly.
 Figure 2. Number of bumped wafers by technology in a) 2000 and b) 2005. (Source: Prismark Partners) |
This can be understood by looking at the packaging roadmaps that depend heavily on the market applications.
The National Electronic Manufacturing Initiative (NEMI) has categorized these into the following product sectors:
- Low-cost: Less than $300 (consumer products, microcontrollers, disk drivers, displays)
- Hand-held: Less than $1,000 (battery-powered products, mobile products, hand-held cellular telecommunications)
- Cost-performance: Less than $3000 (notebooks, desktop personal computers)
- High-performance: More than $3,000 (high-end workstations, servers, avionics, supercomputers)
- Harsh (under-the-hood and other hostile environments)
- Memory (DRAM, SRAM).
 Figure 3. Wafer-level CSP redistribution layer. |
The number of I/Os is one of the most important criteria for the selection of the most cost-effective and reliable packaging technology. In 1999, the International Technology Roadmap for Semiconductor (ITRS) proposed 120 to 600 I/Os for low-cost and hand-held applications, up to 1,400 I/Os for cost performance, and 3,200 I/Os for high-performance applications (Table 1), coupled with an on-chip performance of up to 2 GHz by the year 2005 for both cost- and high-performance products. The number of bumps for flip chip technology will increase because of the electromigration limits of the solder interconnects. Because the mean time to failure of a bump is a function of the passivation opening and current, a lower pitch will require more bumps in parallel for power and ground. The 1999 ITRS states that in 2005 (for the 100 nm generation), the cost-performance microprocessor carries an average current of 80 A (96 watts at 1.2 volts). With a bump pitch of 150 µm and a passivation opening of 65 µm, the current limit is 95 mA per bump for an 80°C chip temperature, and 45 mA for a 100°C chip temperature. The voltage and ground current will require 840 bumps each for a total of 1,680 bumps for the supply current if the operating temperature of the chip is 80°C, and 3,550 bumps if the operating temperature is 100°C.
This increasing density of I/Os on the chips has already driven the pitch of peripheral pads down to 70 µm, which is within the capability of wire bonding tools. The challenge with wire bonding lies in the nature of the sequential process. The feasibility is not as much the problem as is the speed to interconnect all chips from a wafer. Switching to WLP allows all chips of a wafer to be bumped or packaged in the same process step.
For high I/O pincount devices, the trend is toward bumping technologies that ensure high yield at a low cost. Current electroplating and photolithography processes for bumping ICs can create 50-µm pitch area array bumps. This high yield technology is also responsible for the strong gold bumping market. The focus in that market is LCD drivers and related applications in which spaces between pads are 10 µm and less. No other technology is able to perform the requirements in that industry.
A redistribution process to enlarge the pad pitch of the ICs is a common step for all wafer-level CSP technologies (Figure 3). Because the size of the chip defines the size of a WL-CSP, the required ball pitch is a function of the I/O count and die size. The ball pitch for all WL-CSP approaches is more than 0.4 mm, so this limits the possible I/O count. Therefore, the main applications of WL-CSP are low- and medium-pincount devices, as shown in Figure 4. As a consequence, the strongest drivers for WL-CSP are in the memory, automotive and low-cost consumer markets.
Ultimately, cost is the main driver for wafer-level packaging technologies, and a simple cost model can be useful. A peripheral bond pad density of 2 pins per square mm (such as 200 pins for a 10 x 10-mm chip) is assumed. The cost limit for an established single chip package (SCP) is approximately one cent per I/O. This means approximately $300 per 150-mm wafer and $550 per 200-mm wafer, assuming nearly 100-percent yield for IC process and redistribution. This is much higher than the cost for thin film redistribution and bumping in volume production. As long as the device yield on the wafer is reasonable, the extra cost of packaging bad ICs - which happens when whole wafers are processed - is not significant. Testing of the die can be done after redistribution and bumping. The result is known good packages instead of known good die, further reducing total cost.
300-mm Process Challenges
Many wafer bumping and wafer-level packaging technologies use electroplating, which is a relatively expensive but reliable technique that allows fine-pitch solder bumping or copper redistribution layers for CSPs. In Japan, in particular, electroplating is also used for building up copper posts in certain WL-CSP designs. A cheaper alternative to electroplating is the photo-stencil process for forming solder balls, and aluminum sputter plus etching for realizing redistribution traces. Whatever technology a company starts with, it is probably wise to make tool decisions (especially those for the photolithography steps) in such a way that they allow both electroplating and photolithography processes. What follows is a closer look on how electroplating and photolithography depend on each other.
Reliability of electroplated solder bumps is highly dependent on the under bump metallization (UBM). Electroplated solder bumps are made by passing current through a full, thin metal layer on the wafer, which acts as the seed layer for the electrodeposition. The requirements for the seed layer are good homogeneity and an adhesion to the die metallization and passivation that guarantees high reliability. To prevent interdiffusion of the seed layer metal into the die metallization, a barrier is deposited underneath the seed layer. All metal oxides of the wafer metallization have to be removed before the metal deposition to guarantee a good electrical contact. This is done by back sputtering or ICP etch in the sputtering tool, just before the metal is deposited. The UBM layers can be deposited with high yield and excellent uniformity on 300-mm wafers using existing IC sputtering tools.
 Figure 5. The first plated (not optimized) 300-mm wafer before reflow. This is a test chip with different I/O configurations. |
300-mm cluster tools have enough flexibility for different metal stacks, and short process times reduce cost. The shape of the metal structures is determined by the resist mold, which has to be uniform over the entire wafer. A sufficient depth-of-field is necessary to structure thick resist layers (100 µm and higher). The photoresist should have a clear edge bead removal (EBR) zone around the outer edge of the wafer, beyond any active devices. The EBR zone is necessary because the current for the electroplating process has to be applied to the seed layer along the entire perimeter of the wafer to guarantee a homogeneous current distribution. The EBR can easily be realized using full-field mask aligners with the EBR pattern integrated into the photomask layout.
In addition to the EBR, single-wafer plating systems require protection on the wafer backside. An elastomeric sealing ring over the resist edge prevents edge plating to give more uniform bump height distribution. A stepper that operates in high throughput mode would also print the reticle patterns over the wafer edge. This often creates problems because the electrolyte can then leak through bump molds under the sealing ring and deposit at the electrodes and the wafer back. The reduction in throughput required to avoid printing over the wafer edge makes the use of steppers expensive.
 Figure 6. Height distribution of Photo-BCB on a 300-mm wafer. |
With a full-field mask aligner, all dice and necessary auxiliary structures can be exposed in one shot. Besides the basic requirement for the plating process as described above, such auxiliary structures could be dummy bumps at the wafer edge that give a uniform current density through the plating mask and, therefore, improved bump height uniformity across the entire wafer. Or, there can be need for mechanical support at the wafer periphery during backgrinding, which requires certain bump configurations close to the wafer edge. Such requests severely impact throughput for 1:1 steppers. At this stage, a synergy between the sputtering, photolithography and electroplating processes is an essential factor to produce a high-yield process.
In the case of WL-CSP, photolithography is used to pattern the high-density runners on the dielectric layer, the vias through dielectric insulation layers and the mold for electroplating or photo-stenciling the ball grid array. The metallization of the runners can be made by either electroplating or by sputtering and then etching, depending on the metal used. The requirements for UBM are the same compared to bumping technologies.
Initial WLP Results
In April of 2001, the SECAP consortium ran 300-mm wafers for both bumping and redistribution processes through the tools of the member companies. Results were validated by the Fraunhofer IZM in Berlin, the application center for 300-mm development, where tool qualification is performed for users of advanced packaging equipment. The first plated wafer, using high-lead solder plated at a rate of 4 µm per minute, produced across-wafer uniformity of less than 10 percent or ± 2 µm (3 s) before process optimization. A SEM of these bumps before reflow is shown in Figure 5.
The SECAP members, together with the Dow Chemical Company, also tested Photo-BCB for IC passivation. A BCB layer was deposited and structured on 300-mm monitor wafers, with a height distribution of ± 0.08 µm over the full 300 mm (Figure 6).
The SECAP consortium successfully demonstrated that demanding electroplating and photolithography applications are feasible on 300-mm wafers. These results are important for implementing WLP on 300-mm wafers, a technology that will become increasingly critical as the industry completes the transition to 300-mm IC processing. AP
Michael Töpper is the head of wafer-level packaging and Herbert Reichl is director at Fraunhofer IZM (Berlin). Paul Siblerud is general manager of advanced packaging and Gary Solomon is technology integration manager, advanced packaging division, at Semitool (Kalispell, Mont.). Hans Auer is head of the advanced packaging business unit at Unaxis. Jim Quinn is vice president of sales and marketing at Image Technology. Dietrich Tönnies is product manager for mask aligners and Elmar Cullmann is senior scientist at Karl Suss. For more information, contact Michael Töpper at Fraunhofer IZM, Gustav-Meyer-Allee 25, D-13355, Berlin, Germany; 49-30-46403-603; Fax: 49-30-46403-123; E-mail: [email protected].