Technology comparisons and the economics of flip chip packaging
03/01/2001
Flip chip
The decision to use flip chip packaging is not a simple one. Many equipment, product, and process variables affect the relative merits of flip chip vs. wire bonded packages. A detailed analysis of all of these factors can help to guide the decision and clarify the effects of the variables on the cost of different packaging approaches.
Wire bonded packages have been used for many years, and today more than 95% of all packages assembled are with wire bonding technology, primarily because the high-speed wire bonders meet most of the interconnection needs of semiconductor devices. However, the past few years have witnessed an explosive growth in solder bumped flip chip ICs on low-cost organic substrates, and the growth will be more than 20%/year by volume over the next five years, according to TechSearch International, a consulting firm that specializes in advanced packaging. This growth is a direct result of the requirements of greater package density and higher performance, as well as the limitations of wire bonding. In comparison with wire bonding technology, flip chip technology provides higher packaging density (more I/Os), higher performance (shorter possible leads, lower inductance, and better noise control), smaller device footprints, and lower packaging profile. The advantages and disadvantages of the two technologies are presented in the table on page S20.
Is flip chip cost-effective?
Once an engineer decides that the performance advantages of flip chip outweigh the benefits of wire bonded BGA/CSP packages and has addressed the logistics of changing over to flip chip technology, he/she then needs to consider whether flip chip is a cost-effective solution. What is the cost comparison between a solder bumped flip chip package and a wire bonded BGA? The answer to this frequently asked question is not simple.
 Figure 1. Process flow for flip chip BGA and wire bonded BGA/CSP packaging. |
The cost of flip chip packaging depends on many factors, which can be categorized as: die and wafer-level issues, type of flip chip bumping technology used, die cost (e.g., microprocessor vs. memory), package assembly flow, and process cost of ownership.
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Under each of the above headings, there are many variables that affect the final flip chip packaging cost. Let us review each one and see with a sample calculation the cost of flip chip packaging compared to BGA/CSP packaging. Similar cost comparison calculations can be made to compare flip chip and other packages, such as TQFP, PLCC, or TSSOP.
Die and wafer-level issues. The flip chip bumping process is a wafer level process, and therefore any cost comparison with a wire bonded BGA/CSP type of package must be done from the wafer level. For example, the number of die on a wafer depends on the bond pad pitch and bond pad configuration on the die. A large bond pad pitch can force a die to be larger to accommodate the bonds, which results in fewer die/wafer. Similarly, if the bond pads are configured in a peripheral format or staggered format, then the die size can be much bigger compared to an area array format on the die. The bond pad size and configuration can have a direct impact on the number of die that can fit on a wafer.
 Figure 2. Wafer information for flip chip BGA and wire bonded BGA/CSP packaging. |
Die yield at wafer level. When the wafers are subjected to wafer-level electrical testing, the products with lower die yield will have a significant impact on the flip chip packaging cost. If the wafer's electrical yield is low, more wafers need to be bumped to achieve the same production volume of the final packaged device. With wire bonded packages, only the devices that are identified as good at the wafer level go through the packaging process. This screening is not possible with wafer-level packaging approaches.
Type of bumping technology. Today there are five major types of bumping technologies: screen printed, electroplated, electroless, evaporated, and solder bump with wire bonder.
There are technical and economic advantages and disadvantages with each of these bumping technologies. For example, screen-printed solder bump technology is an economical process technology, but the minimum pad pitch has to be 150µm. Conversely, the evaporated bump technology can give very fine pitch area array pads, but the cost of the process is very high.
Impact of cost of die. Since the bumping process is at the wafer level, yield losses at the wafer bumping step will increase the cost of the flip chip packaging process. The wafer bumping yield loss could be due to many things, including: the wrong process, different materials, bump height nonuniformity, low bump shear strength, broken wafers or die, solder bridging, and missing bumps.
One must recognize that any bumping technology requires significant effort to optimize it for any particular wafer technology. It should also be noted that solder bumps are not reworkable. Bumping has to be right the first time.
 Figure 3. The cost of a wire bonded BGA/CSP packaging approach is affected by a) equipment availability, b) equipment throughput, and c) variable costs. |
Assembly process flow. Flip chip bumped die can be assembled into final products either by direct chip attach (DCA) or by assembling as a BGA package (FCBGA). The use of bumped die as DCA is still not very common. FCBGA is today more common. The assembly process flow for FCBGA is shown in Fig. 1, along with wire bonded BGA/CSP flow. Generally speaking, the number of processes is an indication of the packaging assembly cost.
Process cost of ownership. One can calculate the cost of flip chip packaging compared to wire bonded BGA/CSP, taking into consideration the process cost of each approach. Each assembly process has a cost associated with it, which depends on: production volume, equipment cost and depreciation schedule, equipment uptime and availability, equipment throughput, fixed costs, manpower cost, variable cost, and yield cost.
Estimation of packaged device cost
From the above discussion, we can see that the comparison of costs between a flip chip BGA and wire bonded BGA is not a simple calculation, but involves a host of parameters that need to be incorporated, beginning from the wafer level. The actual cost of the final package is a combination of all the above costs.
Let us take an example and study the variation in packaging cost for FCBGA and wire bonded BGA as a function of variables such as die cost, number of I/Os, wafer level die yield, and assembly process yield.
Suppose we consider a wafer with a diameter of 200mm, 200 I/Os on each chip, $5 average die cost, and an expected die yield at wafer-level electrical testing of 60%. Now let us compare the packaging cost of a FCBGA package with area array bumps with a pitch of 150µm, and a wire bonded BGA with peripheral bond pads with a pitch of 80µm. The values are all entered in Fig. 2. One can see the number of possible good die on a 200mm wafer.
 Figure 4. Summary of the cost for each process step for flip chip BGA and wire bonded BGA/CSP packaging. |
Suppose we have a planned production volume of one million devices/month, and the packages have to go through the assembly processes as described in Fig. 1. We can calculate the total assembly cost of packaging. The cost of each process depends on the previous process and the yield obtained from that process. Let us take the example of the wire bonding process and calculate the process cost.
The wire bonding process requires a wire bonder at a cost of approximately $100,000/machine with a life of five years. Major contributors to process cost are equipment uptime and availability, which depend on mean time between assists (MTBA); mean time to assist (MTTA); mean time between failures (MTBF); mean time to repair (MTTR); scheduled maintenance time; standby time; and production change-over time (Fig. 3a).
The equipment throughput depends on factors such as bonding speed, pad recognition time, device handling time, lead count (in the case of wire bonding), and expected process yield (Fig. 3b).
The variable cost is calculated taking into consideration the length of the gold wire, the cost of gold wire, capillary life, and capillary cost (Fig. 3c).
When similar process cost calculations are performed for all processes in the flow, one can obtain the total cost of the package. The result is shown in Fig. 4.
Effect of die cost, I/O count, and die yield
An analysis of the dependence of packaging cost on die cost is shown in Fig. 5a for three different values of assembly yield (99%, 99.5%, and 99.9%). As the die cost increases, the cost of packaging increases, and when the die cost is $20, the flip chip BGA cost with a 99% assembly yield is three times higher than a wire bonded BGA/CSP with a 99.9% assembly yield.
At lower I/O counts, the wire bonded BGA/CSP is an economic solution, but as the I/O count increases, the cost of wire bonded packaging increases dramatically. The cost-effectiveness of flip chip vs. wire bonded approaches is a strong function of the number of I/Os on the chip (Fig. 5b).
 Figure 5. Cost/package for three values of assembly yield as a function of a) die cost, b) number of I/Os, and c) die yield at wafer level. |
If the true die yield increases (higher number of electrically good die on the wafer), the flip chip package cost decreases. Figure 5c shows that as the yield increases from 40% to 80%, the cost of FCBGA is reduced by almost 20%. The impact is higher at higher assembly yields. The wafer level die yield has almost no impact on wire bonded BGA packages.
Conclusion * The change-over from existing wire bonded BGA, CSP, TQFP, or TSSOP packages to flip chip packaging needs a thorough cost analysis. Factors that need to be considered include bond pad pitch, bond pad configuration on the die, die yield at wafer level, die cost, bumping technology, the assembly flow, and the process cost of ownership.
Many decisions, such as bond pad pitch, bond pad configuration, and type of bumping technology, need to be made before the die is even designed. Therefore, it is highly recommended that software available in the market be used to analyze the impact of all of these variables to make an educated decision about when to implement flip chip technology.
Acknowledgments
The authors thank Keshav Prasad for his assistance with software design and Ashwini Pradhan for her assistance with software quality testing and validation.
Shankara Prasad, APT Interactive, 235, 40th Cross, 5th Block, Jayanagar, Bangalore, 560 041 India; ph 91/80-665 7277, fax 91/80-663 9214, email [email protected].
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