CSPs, stacked packaging proliferate

07/01/2002

By Jeffrey C. Demmin

Several announcements by major semiconductor manufacturers indicate the extent to which advanced packaging technologies have permeated mainstream products.

Micron Technology announced that its new 256-Mb SDRAM family is using wafer-level chip scale packaging (WLCSP). The WLCSP process includes a redistribution layer and solder bumps. The products will be provided to customers in both wafer format with a wafer map identifying the good devices, as well as in singulated format with fully tested and burned-in die. The latter format can be shipped in tape-and-reel format or in JEDEC trays.

Meanwhile, Amkor Technology Inc. announced that it has qualified a new series of stacked CSPs, with two chips stacked in a low profile, 1-mm thick format. The two-die stacked CSP uses low-profile wire bonding, thin die and a thin spacer. Ted Tessier, Amkor's VP of its advanced applications group in Chandler, Ariz., said that Amkor is delivering customer samples of these devices with 75-micron thick die. Tessier also noted that Amkor has a recent design win for a three-chip stack of logic and memory chips.

Also in the stacked chip arena, Fujitsu and Integrated Silicon Solutions Inc. (ISSI) announced that they are collaborating on stacked multichip packages (MCPs) with combinations of flash and SRAM chips. The MCPs are in fine-pitch ball grid array format, and typical applications are portable devices such as cellular phones and handheld PCs.

In a separate announcement, Fujitsu revealed that it is using a new chip-thinning process that results in 25-micron thick chips. This capability enables MCPs with eight stacked devices. According to Fujitsu, the new thinning process is a polishing technique that does not involve chemicals.

Motorola's latest stacked packaging developments are being implemented in Bluetooth applications. The technology uses low-temperature co-fired ceramic (LTCC) plus stacked RF and baseband ICs. The LTCC substrate includes embedded passives, which decreases the number of components and minimizes the board space. The ability to stack RF and baseband chips avoids the compromises found in single-chip solutions. By keeping the chips separate, they can be manufactured with the optimal wafer processes for each device, in this case 0.35-micron RF BiCMOS for the RF transceiver and 0.18-micron CMOS for the baseband processor. This is an example of advanced packaging technology allowing the chips to be made more cost-effectively than they would be if standard packaging technology had to be used.