10th Anniversary Insights
New (?) and emerging (?) technologies
07/01/2002
BY BILL GREIG
Today, packaging and assembly of integrated circuits (ICs) can be characterized as an aggressive ongoing development effort. From the introduction of the IC in the mid-1960s to roughly into the mid-1980s, the role of the packaging was essentially no more than a carrier and enclosure for the IC and a means to connect it to the outside world. The package made handling and subsequent testing and placement onto a printed circuit board (PCB) relatively simple. Today, however, we need to be concerned with providing not only the "package" - the physical enclosure - but also something that fully supports and addresses the electrical, mechanical and thermal requirements of the IC.
 (1.a) |
To accomplish this, there are many "new" technologies emerging. We are presented with a wide range of packaging and assembly options and the associated "buzz" words and acronyms, including flip chip (FC), wafer-level packaging (WLP), chip scale packaging (CSP), system-in-package (SiP), known good die (KGD) and finally 3-D packaging.
But are these actually "new" technologies - or just old technologies with new names? Let's take a look.
Flip Chip and Wafer-level Packaging
Flip chip is a good example of a modern emerging technology. It is general knowledge, though, that flip chip actually was first introduced into manufacturing by IBM back in the 1960s. Today, however, flip chip is proliferating because it has so many outstanding features that are currently looked upon as enablers that accommodate high-pin count and high-performance ICs.
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With flip chip assembly, multiple devices are typically attached with all connections made at one time, thus providing a low-cost, high-volume assembly process. Because there is no "package" per se, it occupies the absolute minimum space while providing significant improvement in electrical performance and robustness.
Early on, the bumping process for flip chip assembly was accomplished while the chips were in wafer format. Today this is referred to as WLP and is considered as the new cost-effective packaging technology that yields the true die size "package-less package." It's as old as IBM's flip chip technology, though.
Chip Scale Packaging
A CSP is often defined as a package that is no more than 1.2 times the area of the die. Looked upon as a new and emerging packaging technology, it represents the continuing trend of making the package as small as possible. This trend has been in vogue since the earliest days of the transistor.
Figure 1a is a schematic drawing of an early transistor package that was introduced in the 1960s. The leadless inverted device (LID) was developed primarily for use in early hybrids and was intended to eliminate the difficult tasks of working with bare die. LIDs provided a much smaller package format and could be fully tested before assembly, which was by solder reflow. Figure 1b shows a hybrid circuit with LIDs containing transistors, diodes and power transistors that are solder attached to a ceramic substrate.
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The LID was really the first surface mount device and a pre-cursor to the CSP. Figure 1c shows similar LID type packages for both multichip transistors and low I/O count ICs. These packages are still in use and are currently manufactured by Micro Nova Technologies.
System-in-Package
SiP is a multichip assembly in which bare, unpackaged die are interconnected on a common substrate. This assembly provides complete system functionality. SiP has an interesting ancestry. It is a direct descendent of the multichip module (MCM), which came to the forefront in late 1980s and early 1990s. Of course, the MCM is really nothing more than an advanced hybrid circuit. The history of the hybrid circuit goes back to the 1960s. Figure 2a shows a hybrid consisting of transistors and diodes interconnected on the same substrate providing a fully functional circuit. When ICs became available, they replaced the discrete transistors and diodes. And, each new generation of ICs replaced previous generations. About the time when very large scale ICs emerged, the hybrid circuit became a MCM!
Figure 2b shows a SiP. It is a hybrid, and it is an MCM. The history of multichip packaging is long and continuous.
Known Good Die
The term KGD was coined in the late 1980s. It was used to describe bare unpackaged die that were identified to be "electrically good," therefore meeting the same electrical specifications as fully tested packaged devices.
 Figure 3. Bare die test carrier from the 1970s, an early KGD technology. |
Clearly, packaged devices are normally fully tested and are guaranteed to be electrically good. Bare die, however, are usually electrically tested while still in wafer format before singulation. Full electrical testing at this stage is not done. Therefore, when bare die are purchased, there is no guarantee that all die are electrically good and to specification.
This presents a serious problem for any multichip packaging approach because defective die cannot be identified until the assembly has been fully populated and subjected to an electrical test. The effect on the package yield can be devastating. The lack of KGD has been identified as arguably the largest obstacle for implementing cost-effective MCM/SiP applications.
But the lack of KGD has been a problem ever since the advent of more than one die in a package, such as the hybrid circuit. It has become more of a problem when dealing with ICs of ever-increasing complexities, as is the case with MCMs.
Today, however, KGD can be purchased directly from most semiconductor manufacturers or from die suppliers. The bare chips are typically placed in temporary carriers to allow for full electrical testing and in some instances "burned in" before shipment.
Is KGD New? A pre-assembly test procedure for bare die was developed and put into manufacturing by RCA on the Trident Program in the 1970s. Initially, the multichip assemblies, typically with 10 to 15 beam leaded ICs on a substrate, experienced unacceptable yields clearly attributable to electrically defective die - a problem that needed to be addressed.
Bare die were pre-assembly tested using a "carrier" that enabled full electrical testing and burn-in to be realized. The beam leaded ICs were placed in specially designed carriers that were identical to the carriers used for testing packaged devices (Figure 3). Again, this decades-old KGD technology is strikingly similar to much more recent technologies that have enabled significant strides in multichip packaging applications.
3-D Packaging
Whether servicing the low- or the high-end product sectors, the packaging engineer strives to address the need for "smaller, faster, cheaper" products. Many packaging technologies have provided significant size reductions in the X and Y dimension - but where to go next? Obviously, the Z-direction! A new technology? Not really.
It is interesting to see what the early transistor engineers in the late 1950s did on the "Micromodule" Program at Fort Monmouth. Figure 4 shows an innovative approach to high-density packaging - the Micromodule stacked active and passive elements interconnected in the Z-direction. Given the similarity of today's 3-D packaging, you wouldn't guess that RCA's came four decades earlier.
To summarize, there is a song title that really says it all: "When Everything Old is New Again." Let's hope that packaging engineers are somewhat aware of their industry's past. It is clearly related to the present and the future. AP
Bill Greig, can be contacted at Greig Associates, P.O. Box 355, Somerville, NJ 08876; Tel/Fax: 908-707-9466; E-mail: [email protected].
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