Issue



Stacked fine-pitch BGA packages


06/01/2002







Addressing high-density memory requirements

BY ANDREW C. ROSS


Illustration by Gregor Bernard
Click here to enlarge image

With the increasing performance of today's semiconductors and the associated reduction of design and operating margins, every aspect of modern systems is scrutinized to make sure nothing is being compromised, including the package around the die. The impact of this is now being seen within the memory industry. With the advent of DDR333, we see the first main memory technology that requires a fine-pitch ball grid array (FBGA) package to allow it to operate within certain systems. The FBGA package, because of its small size, has reduced connection parasitics. These allow the high-performance memory devices to operate within high-device count workstation and server applications.

The article introduces the FBGA package and shows a solution for stacking it. Stacking is a critical requirement for high-density registered dual in-line memory modules (DIMMs).

FBGA Packaging
The FBGA package is a small ball grid array (BGA) package. The advent of the chip scale package (CSP) concept spawned many variations of interface design. Figure 2 shows the basic configuration of the BGA package. It is constructed of a substrate onto which a die is mounted and an array of balls is attached. Ultimately the die is encapsulated for protection. A basic FBGA essentially uses the same structure but reduces the size of the substrate, as well as the pitch and size of the balls. There are a number of configurations of the FBGA package (Figure 1), and they all maintain the same ball interface but use a modified die connection method.


Figure 1. Several variations on BGA packaging.
Click here to enlarge image

The most recent definition from JEDEC requires the pitch of the balls to be 0.8 mm or less for a package to be called an FBGA. This defines a maximum ball size of 0.4 mm and an overall maximum package height of 1.2 mm. Manufacturers are looking at establishing a standard set of package outlines that do not necessarily relate directly to the die size. With this focus on interchangeability and module standardization, a standard set of mechanical outlines has a number of advantages.

Driving Forces for FBGAs
In the memory arena, size and performance are everything. The FBGA package allows manufacturers of the most advanced SDRAM and DDR SDRAM devices the best of both worlds - a near chip size package with minimal impact on the performance of the device. With the existing thin small outline package (TSOP) packaging, standard body sizes and inductance issues with the leadframe cause signal integrity problems when using high-speed SDRAM devices in large memory arrays.

These issues have forced the introduction of the FBGA package to the PC133, DDR333 and DDR400 memory families. Although standardization of the packages is not yet complete, JEDEC is in the process of establishing a number of standard outlines, ball-array patterns and pin-outs, including 54, 60 and 90 ball versions. Already MO-205, MO-225 and MO-233 have been established as standard outlines (available at www.jedec.org) with many more being established through the standardization process.


Figure 2. Typical BGA construction.
Click here to enlarge image

Beyond the device demands, there have been some recent changes in the application base that benefit from the use of FBGAs. For example, the popularity of the 1U server form factor has placed severe mechanical demands upon memory module designs. Manufacturers are being forced to abandon the traditional 1.7-inch tall registered DIMM in favor of a 1.2-inch or smaller form factor. In the interests of inventory management and simplification of configuration management, the trend has become to move all new registered DIMM designs to the 1.2-inch form factor. The FBGA package offers a more compact footprint and provides some relief for the module designers and manufacturers.

The new 1.2-inch RDIMMs are pushing the placement and manufacturability limits, especially with the high-device count modules. With the 18 and 36 device modules needed for servers, the module designers are forced not only to place 18 TSOP II device sites for the memory, but they have to include clock buffering and signal registers, plus the necessary signal conditioning and power supply filtering. Although JEDEC is very close to providing standard module designs for these configurations, they have yet to be viable solutions.

A new application space helping the case for the transition to FBGA is the PDA and hand-held system market, where space is the most important design consideration. To meet the needs of this market, a new form factor for modules has emerged. This very small module, called the micro-DIMM, is half the size of a traditional small-outline DIMM (SoDIMM) and is able to use only two TSOPs in its preferred mechanical configuration and a maximum of four in an oversized version.

Differentiating FBGA Packages
Because each memory density and technology may have differences, it could appear difficult to establish a valid set of metrics to review the packaging technologies. However, looking at the 54 or 66 pin TSOP II, the mechanical configuration is basically the same. SDRAM and DDR also have very similar demands in terms of interface. Table 1 outlines the differences between TSOP II and FBGA packages in the context of memory applications.


Figure 3. Cross-section of stacked BGAs.
Click here to enlarge image

The main differences are in body size and pin parasitics (Table 1). Stacking has become the industry standard method of creating 36-device modules for high-end applications; it enhances the electrical and timing characteristics of the board and provides an acceptable form factor. Without stacking, the FBGA package will not be able to provide the required densities for the highest capacity memory modules. Stacking for TSOP II devices has been used since the mid 1990s and has successfully enabled 256MB, 512MB, 1GB and 2GB RDIMMs for the workstation and server markets.

All of the current stacking technologies used for TSOP II applications are unable to transition to the FBGA package and provide a viable solution. This is because all rely upon the gull-wing lead of the TSOP II to provide all or part of the Z-axis interconnect. The ball array of the FBGA makes all of these technologies obsolete. Because of this, the emerging PC2700 RDIMM specification does not include a two-bank, x4 (36 device) based module design.

Challenges of Stacking FBGAs
As mentioned earlier, all of the current stacking technologies rely upon the gull-wing lead to form part or all of the Z-axis interconnect (Figure 4). The gull-wing leads stick out from the body of the TSOP package, making creation of the structure relatively simple when compared to a similar structure for the FBGA interface. Because an FBGA uses a small diameter ball positioned under the body of the package, there is no lead that can be used to create a Z-axis connection. To access the signals, it would be necessary to either go through the package or bring the signals to the edge.


Figure 4. Approaches to stacking TSOPs.
Click here to enlarge image

Given the manufacturing issues associated with an FBGA, it is necessary to consider the final application. The finished stacked components are assembled onto a module or a motherboard, and both of these require the stack to be soldered in order to make a connection. During this reflow process, both the final interface and the eutectic solder balls on the bottom of the FBGA will also reflow. Any mechanical disturbance of the device will compromise the integrity of the FBGA stack. All of these issues make the development of an FBGA stacking technology non-trivial.

A New FBGA Stacking Approach
When developing new FBGA stacking technology, we found it was important to consider the following principles:

  • No pre-processing of the FBGA devices.
  • All manufacturing equipment will be standard off-the-shelf.
  • The base materials added to the stack will be widely available.
  • Design rules used and features incorporated will be widely available from multiple suppliers.
  • The manufacturing process will be device-anonymous.
  • The manufacturing process must be scalable and transportable.

Based on a panel stacking approach, these products use a tetra functional substrate material to provide both mechanical spacing and electrical interconnect for the stack. Figure 3 shows a cross-section of a typical stack.


Table 1. Comparison of TSOP II and FBGA packaging.
Click here to enlarge image

There are three basic elements associated with the FBGA technology:

  • Transposer - A planar substrate used to mount the FBGA and route signals to and from the Z-axis interconnects.
  • Interposer - Typically a ring, this element serves to provide a mechanical spacer between device layers (transposers) and is the main transport for the Z-axis interconnects.
  • Interface - An enhanced transposer, this planar substrate not only carries an FBGA but also provides a surface for the positioning of the system-to-stack interface. Typically this will mimic the FBGA and be placed at the base of the stack.

Associated with the basic elements are the structures that provide the connections to and from the FBGA packages and create the Z-axis interconnects and element-to-element connection. These include:

  • Filled vias - Used to create the Z-axis interconnect within the interposer.
  • Unsupported solder columns - Used to create the connections between the transposers, interposers and interface layers.
  • Peripheral pad array - The pattern used to form the Z-axis interconnects between layers.
  • Device cavity - The space created by the interposer into which the FBGA fits.

All of these elements and features combine to provide a versatile packaging technology. The resulting features for the users include:

  • The use of transposer layers provide for the inclusion of solid power and ground planes for FBGA devices above the main system board. This serves to reduce power connection inductance and aids in reducing power supply noise.
  • Multi-layer transposer layers offer impedance control of critical signals within the stack structures.
  • Transposer layers allow for advanced signal routing to enable line length balancing, required for high-speed applications such as DDR333, DDR400 and SyncSRAM.
  • Transposers provide for significant rerouting of signals, allowing advanced configurations to be constructed, including wide data busses, monolithic emulations, optimized interfaces, and heterogeneous stacks.
  • The peripheral pad array provides significant Z-axis connection bandwidth allowing the application of the base technology to an extremely wide range of memory and other devices.
  • The final interface layer provides flexibility in the final interface configuration. Options include varying ball sizes, counts and arrays, leaded and leadless interfaces, and emulation of the base component interface.
  • The device cavity allows for a great deal of flexibility in the design of the stack. Because the cavity size can be independent of the FBGA size, a single design can be used for multiple applications.

Future Work on FBGA Stacking
Future expansion of the technology will include increased Z-axis bandwidth and signal density, as well as optimization of the technology configuration, including reduction of the stacking footprint overhead inclusion of passive devices (such as decoupling capacitors and termination resistors into the stack, reduction of the overall height of the stack, and an increase in the number of device layers). All of these enhancements will expand the application base for which this technology is appropriate.

As of today, a viable solution for the high device count DDR modules exists. The application of the FBGA stacking technology will allow the latest generation of servers and workstations access to the highest performance memory technologies, without compromising the amount of memory available. AP

Andrew C. Ross, director of technology, can be contacted at DPAC Technologies Inc., 7321 Lincoln Way, Garden Grove, CA 92841; 714-898-0007; Fax: 714-897-1772; E-mail: [email protected].


null

Common abbreviations and definitions
DDRDouble Data Rate : An SDRAM with a data bus capable of issuing data on both the rising and falling edges of the device clock.
DDRIIA second generation DDR device specification being standardized by JEDEC. This specification includes 400 and 533 Mbit/sec transfer rates.
DDR333A DDR memory specification and device standard established by JEDEC with a data bit rate of 333 Mbits/sec.
DDR400A DDRII memory specification currently being standardized by JEDEC with a data bit rate of 400 Mbit/sec.
DIMMDual-in-line Memory Module: The standard form factor memory used in systems.
MicroDIMMA very small outline DIMM used by ultra portable electronic devices (PDA, phone, MP3 players).
PC133An SDR memory specification and device standard established by JEDEC with a data bit rate of 133 Mbits/sec.
PC2700A DDR DIMM specification and standard established by JEDEC with a data bandwidth of 2.7 Gbytes/sec. The modules are based on DDR333 memory devices..
RDIMMRegistered DIMM: A DIMM with registers and clock redrivers, required for modules with high device counts, typically 18 or higher.
SDRAMSynchronous Dynamic Random Access Memory.
SDRSingle Data Rate: An SDRAM with a data bus capable of issuing data on only the rising edge of the device clock.
SoDIMMSmall Outline DIMM: A small form factor memory module used predominantly by the mobile systems (laptops, notebooks).
TSOPThin Small Outline Package: A small profile package adopted by the memory manufacturers as the standard package for most memory types.
TSOPIIA version of the TSOP package that has leads on the two longest sides of the package. This package is the preferred type for SDR and DDR SDRAM memory.
Tetra FunctionalDescribes an epoxy system for laminates that has four cross-linked bonds rather than two, and results in a higher glass transition temperature or Tg.
TgGlass transition temperature: The temperature at which the laminate mechanical properties change significantly.
Definitions from the San Diego Circuit Board Service Web site (www.sdcbs.com/term1.html).