MEPTEC MEETING REPORT

03/01/2002

Intel's Packaging Plans Discussed

BY JULIA GOLDSTEIN

SUNNYVALE, CALIF. - Rob Willoner presented Intel's bumpless build-up layer (BBUL) technology at MEPTEC's January meeting. Willoner discussed the need for innovations in transistors, interconnects, lithography and packaging required to drive Moore's Law, and he described BBUL technology as part of the solution.

BBUL technology reduces package size and improves performance and power delivery by embedding an integrated circuit (IC) chip within an organic substrate, eliminating the need for solder bumps to connect the chip to the package. Interconnection is made with copper lines in the built-up layers over the chip. The resulting package is about one-half the thickness of a standard C4 flip chip package (not including the pins or bumps on the outside of the package).

The BBUL design also allows decoupling capacitors to be placed much closer to the die, lowering inductance and requiring less total capacitance. Die-package pitch and line spacings are similar to those used in organic flip chip packages. While a bumped chip requires a fixed pitch for the solder bumps, BBUL technology allows the die-to-package interconnects to be arranged in any pattern, giving more flexibility in routing and allowing higher routing density where needed. This advantage can reduce the total layer count by 50 percent. BBUL technology can also be used in multichip applications, combining a microprocessor with a sensor or graphics chip in a single package, for example.

BBUL technology was initially announced in October 2001 and Intel expects it to be available for commercial products in about five years. Intel has not decided whether to eventually license the technology to subcontractors. Because BBUL technology has been demonstrated but not yet used in a product, many issues brought up by the audience during the question and answer session are still under consideration. For example, reworkability has yet to be addressed and reliability data are not available. Simulations have shown that a CTE mismatch between the chip and the organic substrate, of particular concern in a package without underfill, is resolved by using a thin, flexible bond pad.

Willoner admitted that the lack of solder bumps to conduct heat away from the chip "may be a bit of a downside," but stated that external heat sinks should be sufficient. Power consumption and dissipation need to be addressed at operating frequencies increase beyond 10 GHz.

For more details on the BBUL process, Willoner referred the audience to technical packaging articles available at www.intel.com
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