The back-end process: Step 1 - Package design
01/01/2002
BGA design process flow
BY LES AMMANN
As semiconductor devices become significantly more complex, designers are challenged to fully harness their computing power. Package design at the first interconnect level has a major impact on device performance and functionality. At the same time, electronic equipment designers are shrinking products, increasing complexity and setting higher expectations for performance. To meet these demands, package technology must deliver higher lead counts, reduced pitch, reduced footprint area and significant overall volume reduction. This places unprecedented demands on the skills of package designers and the tools they use.
An advanced packaging solution from an electronic design automation (EDA) supplier should use automated approaches to help designers define manufacturing feasibility and optimum performance of a device at the beginning of the design phase.
Step 1: Data Input and Manipulation
The first step to IC package design is getting the information for input. Data is often received in arbitrary formats. The information usually contains die pad coordinate locations (X, Y), pin number, net names for the die pads and sometimes the associative net name to the BGA. If the data is supplied electronically as an ASCII file, then the data can be easily manipulated to the required format by the EDA tool. Some EDA vendors have taken steps to streamline data manipulation by offering ASCII generators, which will easily input the unknown format, manipulate it and output the data into a usable format by the design tool in use. Once reformatting is complete, the design tool uses the information to generate an intelligent database, including die, parts, technology and design rules, from which to start the package design.
Step 2: Technology and DRC Set Up
The next step in the design flow is to load or set up the manufacturing rules for the type of package being designed. Usually at the data input process, options exist to include already developed technologies, pad-stacks, parts and design rules into the design mix up-front so that the design environment is as intelligent as possible. Options also exist within the layout environment to change the technologies during the design to have access to these different rules. This allows the designer to achieve high yields by increasing design constraints for the substrate. It also provides access to other technologies, like build-up substrates to shrink the substrate area for a given device.
 Figure 1. A good list of design rule checks (DRCs) is available in high-end IC packaging tools. |
As for specific IC package design rule checks (DRCs), an advanced EDA tool offers a fairly robust arsenal of manufacturing design rules (Figure 1). These rules may be on-line, which is preferred, or they might all be executed as a batch process at the end of the design. Actually, both are preferred to ensure that the design is sound.
Step 3: Component Generation and Package Re-use
For today's high-end packaging requirements, off-the-shelf packages are typically inadequate. Almost every package has to accommodate a custom device, meaning that it is difficult to succeed reusing an existing package. However, some EDA tools allow automation in this area so package reuse is possible. One approach is to have search programs inside the design tool, which will search a database of already designed packages using a device that is similar to one being packaged. Once a match has been determined, the tool automatically inserts this design, discards the existing device, and inserts and reestablishes wire bonds and nets in accordance with the new device.
Step 4: Bond Wire Fan-out
In any wire bond design, an automated and accurate approach to distributing bond wires on the substrate is critical. Bond wire fan-outs for today's packaging require flexible and interactive automation in the design environment. Automation must encompass the large list of packages on the market, such as PBGA, flexBGA and advanced wire bonded packages (including stacked die and multi-tier BGA packages). A good approach to handle such a list of packages is to use a parametrically driven bond shell function with on-line assembly constraints and manufacturing design rules. This allows complex bond wire fan-outs (Figure 2) to be generated without error in a few minutes.
 Figure 2. A ghosted image of the complete bond shell can be used for visual and instrumental validation by applying distance checks between rings or substrate bond fingers. |
One of the latest developments in bond wire fan-out automation produces the bond shell with the best minimum achievable bond wire lengths; this saves costs in manufacturing by minimizing the amount of gold bond wire used. A parametric bond shell generator also allows many steps to be combined. For example, 3-D wire profiles can be part of the generation so that the bond wire fan-out can be developed in a three-dimensional state.
Step 5: Net List Optimization
In general, IC packaging connection lists can be fixed (such as dictated connections with no flexibility for change) or flexible. Each type usually has four main variations, including: (1) complete net-list (having all connections decided); (2) partial net-list (having some connections decided, usually power and ground nets); (3) open net-list (not mattering how it is connected); and (4) constrained nets (extended data or requirements for high-speed rules, such as differential pairs, cross-talk tolerances and impedance requirements).
High-end EDA tools offer ways to honor all connection requirements and are usually flexible on how to read full or partial connection lists, or to automatically generate connections for open designs. The lists need to be in an electronic form, and ASCII lists work best because they are easily manipulated. Again, ASCII wizards play an important role in quickly reformatting these lists into an accepted format by the design tool. As with high-speed net constraints, these can be read into the design tool so all constraints will be adhered to during routing.
 Figure 3. Many power and ground planes can co-exist in a package design. |
Optimization of the connection list can be accomplished by using functions for setting, swapping, releasing, re-assigning and defining net groups within the design environment. Usually when a design request is received from a user, the connection list is regarded as work in progress. This means that the connection list has not been finalized, and changes are expected throughout the progression of the device. EDA tools offer ways to read in these connection list changes automatically and, if needed, use a net driver or series approach so traces that are already routed can be updated at the same time as the die pins or BGA pins.
Automatic net generation is an effective option for establishing a connection list for some or all pins remaining without a net-list. Design tools usually offer this approach and are based on a shortest line-of-sight algorithm.
Step 6: Conductor Routing and Via Placement
Routing is typically the biggest challenge in IC package design. There are countless problems and solutions for any given design at the physical level alone, and it grows exponentially when high-speed rules and other constraints are introduced. Fortunately, the problem is two-dimensional for the most part. There are three main approaches for routing an IC package, and all of them can be used during the design cycle, depending on the type of package technology being developed.
The first approach is low-intelligence manual routing. This can be tedious or easy depending on function switching, menus and the designer's thought process. This means that the designer has a big part in solving the problem first hand for each trace. Usually starting at a net in the middle of a quadrant of the package, the designer sews the trace from either the ball pin or the die pin from one bend to the next, trying to hug the topology and thinking of the neighboring nets.
The next approach is high-intelligence or interactive routing. This type of interactive approach is less tedious, and this can depend on the router intelligence, function switching and process flow. High-end IC packaging tools offer this effective routing approach, which allows highlighting of the selected net routing path for a visual goal. Such design tools allow "push and shove" of neighboring traces and vias and automatic clean up of un-needed vertices or bends. They also allow a selected net to follow the path it sees, eliminating tedious point-to-point routing.
IC packaging auto-routing algorithms can be very helpful for simple packaging technologies. Router set-up and user interaction are key to successful routing of simple to complex packages. Some current auto-routers can succeed with complex package designs.
Step 7: Ground Plane Generation
Usually, the next step after routing traces on the IC package is the creation of power and ground planes. The number of planes is driven by the number of power and ground nets and sub-nets in the design. Oftentimes there are multiple nets defining a given power or ground plane, e.g. VCC1 and VCC2. These are different sub-nets of the same power or ground net, and they are treated as the same net. This, combined with the need to minimize the number of layers in the design, requires the planes to be split with a defined minimum gap (Figure 3). Power and ground planes are also used as a thermal enhancement, helping to spread the heat generated at hot points in the device. Planes are usually placed internally and on the bottom of the package, but they are also placed on the top layer to help the structural balance of the copper in a package. All of the ground and power nets are connected to these planes through vias. These are usually located on or around the power and ground rings of the bond shell, and are therefore called ring vias. They are spread fairly evenly around the bond shell, with perhaps four to seven per side, depending on the importance of the ratio of power and ground nets to I/O signal nets.
Step 8: Output Reports and Documentation
Once a design nears completion, outputs of various types are needed to verify that the design criteria have been met. Design tools provide various output reports, usually in an ASCII or text-based format, containing important information about a design. This can include bond wire details, net connections, trace lengths and quick RLC information (Figure 4). Additionally, in some advanced design tools, options exist to create a custom report by selecting which topics to add.
 Figure 4. Various types of information about a design can be reported. |
A critical aspect of design is providing understandable images of the design. These can come in various formats including electronic image files, such as data exchange format (DXF), or prints of the completed design. Creating documentation can be time-consuming because of the time it takes to generate the details, notes, views, and drawings portraying the product. It can be difficult to automate this because different types of information can be useful for different designs, which can be a function of the design itself or the designer's preference.
Step 9: Output to Manufacturing
The final step in the design process is to provide an accurate image file output that assembly houses and manufacturers can use. There are three image output types that have become de facto standards for packaging: DXF, Gerber, and graphical data stream (GDSII). DXF and Gerber formats are most commonly used, with GDSII being used for smaller dimension designs such as those seen in wafer-level packaging. Most IC packaging tools offer these outputs in various forms, but each tool set is slightly different in use, accuracy and format. It is useful to test all of the available options when choosing a design tool. Other features that should be checked when looking for a design tool include ease-of-use, process flow, outputs and all design steps for compatibility with in-house and customer requirements. AP
Les Ammann, director of advanced packaging technologies, can be contacted at Zuken USA, 2041 Mission College Blvd., Suite 260, Santa Clara, CA 95054; 408-562-0177; Fax: 408-855-1860; E-mail: [email protected].