New Methods for 3-D Chip Integration
12/01/2003
COMBINING SEMICONDUCTOR PRODUCTION AND PACKAGING EXPERTISE
BY CHRISTOPH SCHEIRING
When a new technology emerges, talk typically centers on more gigahertz, fewer micrometers or higher integration densities. In the background, however, a quiet revolution is taking place in the form of process technologies, manufacturing structures and new forms of collaboration between industry partners. The cause? A high demand for modern semiconductor applications, and escalating cost pressure. Conventional technologies cannot resolve these issues.
Trends and Limitations
The most important demands on microelectronics include more functionality at the chip level, smaller packages, improving time-to-market and greater design security — all at continually lower costs. System-on-chips, a miniaturized and cost-effective response to the first challenge, brought great progress but quickly faced limiting economic factors. This is especially true with embedded technologies for performance enhancement, where at least two different process technologies exist on the chip — such as the combination of high-density logic and broadband high-frequency circuits. Mixed technologies like this can be produced with improved performance at a lower cost by using various chips, each suited for its respective function.
This is where the next challenge comes in, known as the wiring crisis. Connecting multipin chips at the board or substrate level leads to difficult routing and interference, especially with parallel data processing circuits and high-frequency applications. A solution can be found in 3-D stacked chips. Here the boundaries between semiconductor manufacturing and packaging become blurred and require integration of the assembly partner in the product and process definition.
Methods of 3-D Chip Integration
The first stacked chips used components with peripheral connections adhesive-bonded together and connected with wire bonding. This method is still widely used. In effort to develop high-performance, low-cost solutions, the latest approach by Datacon and industry partner Infineon Technologies (Munich, Germany) bundles together semiconductor production with packaging expertise.
The starting point was transferring surface-array pin to the inter-IC level. Contact surfaces for the process were copper squares measuring 10 ¥ 10 µm2 distributed over the chip's surface in a 20-µm grid. The copper squares were connected using a diffusion soldering procedure.
Solid-liquid Inter-diffusion
The resultant bonding technology relies on solid-liquid inter-diffusion face-to-face (SOLID F2F), or a special sintering process to combine two chips with their active sides facing each other.
The surface of the bottom chip is 5-µm-thick copper, while the top chip has a congruent structure of copper that is also covered with a 3-µm layer of tin (Figure 1). Electrical connections are made through 10 x 10 µm2 contact pads surrounded by 10-µm-wide, nonmetallized channels for electrical isolation. The rest of the surface is also metal-coated, forming an electrical barrier between chips to be connected. The chips are congruently positioned and soldered with the tin layer of the top chip. Conventional techniques are used to bond the external input and output connections. This bonding technology forms a contact interface about 10 µm thick, with a contact density greater than 105/cm2 to ensure suitable electrical performance.
 Figure 1. Two-layer stack using SOLID F2F technology |
null
This flat, F2F metal connection is an inexpensive alternative to the increasing connection overhead for planar substrate or board connections. It offers high signal integrity and low crosstalk, avoiding many problems commonly associated with high-frequency circuits.
Precise Production Equipment
Two systems represent the core technology for implementing this chip stacking process. A high-precision flip chip bonder detaches chips from wafer tape, flips them 180 degrees, optically aligns and bonds them to the bottom wafer with a temporary fixing agent that holds the chips in place.
 Figure 2. Flip chip bonder |
null
In the next process step, the bottom wafer is completely covered with the top chips and transferred as one unit to a specially developed chip-to-wafer bonder where it is hard-soldered in a forming gas atmosphere at 270°C. The liquid tin reacts with the copper surfaces and is transformed into the high-melting-point alloy Cu-3Sn. This intermetallic phase is thermodynamically stable, with a melting point of 600°C — ensuring a temperature hierarchy with subsequent processes. In addition, the alloy retains highly suitable electrical and thermal conductivity. The stacked chips are then detached and fed to a conventional assembly process.
Conclusion
As the boundaries between semiconductor manufacture and assembly and packaging become blurred, innovative process technologies demand closer collaboration between the partners involved. It is worth IC manufacturers' time to communicate with their assembly partner at an early stage to ensure they benefit from the most efficient system solutions.
CHRISTOPH SCHEIRING, manager, may be contacted at Datacon Semiconductor Equipment GmbH, Innstrasse 16, 6240 Radfeld, Austria; +43 5337 60 0; e-mail: [email protected].