3-D Packaging Solution for High-performance Memory
08/01/2003
The ball stacked package has proven to be more efficient for device interconnect, and the small component outline and lower profile enables a higher component density demanded by newer market segments
By Vern Solberg and Ignacio Osorio
The new generations of dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM) technologies are contributing to increased system performance significantly. Processing speed improvement, however, can be hampered by inefficiency in both package performance and module-level interconnect. Furthermore, these high-performance memory die have been designed with center bond pads rather than the peripheral bond format more common in earlier applications. The change in die layout, although challenging for traditional leadframe package technology, has proved ideal for array packaging.
The array format package with the die facing down furnishes a much shorter circuit path than leadframe packaged die, minimizing the signal path between die and the printed circuit board (PCB) structure.
For this reason, the developers of Rambus DRAM (RDRAM) and dual data rate (DDR) DRAM have found that array-type packages enable optimized memory performance by furnishing a significant reduction in signal inductance. Memory performance is affected by numerous physical problems such as impedance mismatch and transmission line noise. These problems are further impacted by the long distance that high-speed signals must travel from the memory integrated circuit (IC) to the central processing unit (CPU). Memory devices running at or above 167 MHz begin to experience performance degradation due to excessive line or signal inductance (6 to 12 nH).
By making the interconnection pathways shorter, data travels faster and increases overall memory system performance. Increasing DRAM speed is necessary to facilitate faster processors, but speed alone is not sufficient to alleviate the CPU-to-memory performance bottleneck associated with memory- intensive applications.
Achieving Higher Electrical Performance
With the advent of the center-bond pad die designs, one company* developed a µBGA package** that has contributed to reducing the performance bottleneck. The facedown package methodology proved to be efficient in both area utilization and in minimizing the circuit path length between die and board. Two methods of die-to-package interface are used, wire bond and lead bond. Outwardly, a lead-bonded µBGA package and wire-bonded µBGA package look alike (Figure 1). In either case, when attaching the die facedown to a ball array package substrate, line impedance is reduced and signal speed improves.
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In simulating and modeling the electrical performance of the center-bond memory die package, the company studied two substrate fabrication methodologies, a single copper layer substrate and a two copper layer substrate. In establishing the computer models, the company defined the physical elements of the die, dielectric constants of the encapsulation, the base substrate material properties, conductivity of the copper circuit, and the dynamics of the solder ball contact connecting the package to the circuit board. The second model had the same basic elements with the addition of a second copper circuit layer on the base substrate. The additional layer of copper provides a more efficient ground return, further lowering inductance and reducing the effects of switching noise. The ground plane effect significantly reduced the noise level, but the number of current sinks within the ground plane influenced inductance levels as well. In simulation studies it was determined that ground trace width alone will not decrease inductance significantly; however, a common ground plane can reduce inductance to a level below 0.1 nH, further minimizing noise level within the circuit.
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Increasing Memory Capacity
Unsatisfied with the traditional concept of Moore's Law, OEMs are seeking packaging solutions that can increase memory capacity without the accumulation of additional modules. As a practical and economical solution to increasing memory package capacity the company developed the µZ-Ball Stack Package**, a hybrid of the basic µBGA. An elegant and economical process, the stacking of single array packages on top of one another provides two to four times the memory capacity of the single die alternative. The package sections (or levels) are joined electrically and mechanically with peripherally located solder balls, as illustrated in Figure 2. The ball contacts that interconnect one level to the other protrude a short distance beyond the size of the die (approximately 0.6 mm on each side for a total of 1.2 mm). The peripheral solder balls transfer electrical signals on a direct path between each package level, terminating at the PCB or module surface.
Memory devices typically are furnished as a subassembly or module designed to provide a specific storage capacity. A common application is the grouping of eight, single-die packages (or nine for parity). Adopting a rigid circuit board as its base, the module concept furnishes an efficient method of grouping and interconnecting the memory devices. The most common module configurations in the market are designed to plug into connectors provided on the host PCB. The JEDEC registered single in-line memory module (SIMM), the dual in-line module (DIMM) and the small-outline (SO-DIMM) configuration (developed for portable product applications) are well established in the marketplace. Figure 3 illustrates the dynamics of adapting the ball-stack package configuration in the grouped format, furnishing two to four times the memory capacity of a single die package set.
Generally, the memory packages are arranged side-by-side on one or both sides of the circuit board module and include numerous passive devices and controllers. Several variations based on this format are in wide use for adding memory to computers and other high-end products. The JEDEC memory modules also are used in most server applications in which space limitations and additional electrical requirements demand that the memory module be placed close to the microprocessor. The DIMM design is proving to be ideal for high-end server applications, enabling higher density, uncompromised reliability and enhanced performance. The SO-DIMM variation, on the other hand, provides an economical, high-density solution for mobile applications, furnishing a low profile in a relatively small form factor.
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Package Assembly
The package assembly process for the µBGA is a mature technology, and process yield is high. In the process, die are attached to the substrate base material, wire-bonded or lead-bonded, encapsulated, and electrically tested before stacking. The activation of individual memory die within the stack is controlled through the selection of one of four solder ball contacts that terminate at the module level. It should be noted that the µZ-Ball Stack package technology adapts to the memory module level with conventional SMT assembly processes. The package technology enables the DIMM card to be used individually or combined in multiples to form a larger memory array. The table illustrates the density potential for 256 and 512 Mbit memory when adapting ball stack package technology.
 Figure 3. The µZ-Ball Stack package enables manufacturers to take advantage of the standard DIMM (left) and SO-DIMM (right) format for maximizing memory capacity. |
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 Figure 4. Combining the CPU and memory on a single high-density substrate provides optimal electrical performance and versatility. |
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Conclusion
The higher processing speed of today's electronics requires a direct signal path and interconnection between controller, processor and memory. To meet the criteria for faster processing speeds, the packaging industry will abandon traditional leadframe solutions of the past and adapt a more dynamic approach, one that will minimize the signal path between silicon and circuit board.
*Tessera Inc.
**µBGA and µZ are trademarks of Tessera Technologies Inc., San Jose, Calif., and represent patented methodology and packaging material sets.
VERN SOLBERG, senior applications engineer, and IGNACIO OSORIO, marketing manager for memory business, may be contacted at Tessera Technologies Inc., 3099 Orchard Dr., San Jose, CA 95134; (408) 894-0700; Fax. (408) 894-0768; E-mail: [email protected] and [email protected].