Embedded FPGA Market to Evade Downturn
03/01/2003
Scottsdale, ARIZ. — While current economic conditions will affect all aspects of the semiconductor industry, the impact on the embedded field-programmable gate arrays (FPGA) market should be minimal, according to In-Stat/MDR.
The high-tech market research firm reports that, because this market is still in its early stages of development, it will not experience the same degree of negativity seen in more mature market segments, such as the dynamic RAM market.
In the case of embedded FPGA technology, several companies already have made substantial investments in its development. Investments, while slowing due to general economic conditions, are unlikely to be aborted. The licensing of Xilinx's SRAM-based FPGA core by IBM is an indication of the future importance placed on the technology. The driving force behind growth for this technology will be in meeting multiple system design requirements and applications via the use of a single design approach and using that design for the evolution of next-generation designs.
In-Stat/MDR also has found that:
- Worldwide merchant market dollar shipments of customer-specific, cell-based designs containing block(s) of embedded FPGA are forecast to increase from $2.9 million in 2001 to $603.1 million by 2006. This translates to a forecast compound annual growth rate (CAGR), over the 2001 to 2006 timeframe of 191.6 percent.
- In the embedded FPGA market, as is the case for most other product markets today, communications will represent its largest consumer, with the vast majority of applications being in the networking and telecom infrastructure. The embedded FPGA communications segment will account for an average of four out of every five product dollars consumed over the 2001 to 2006 forecast period.
- On the geographic side, and in the near term through next year, it will be The Americas, followed by Europe, which will control product consumption. Beyond 2003, the roles will be reversed, with Europe controlling consumption. The two regions combined will account for more than 90 percent of all embedded FPGA product consumption throughout the forecast period.
- From a programming architecture perspective, flash architecture will dominate embedded FPGA product consumption due to the architecture's smaller footprint, accounting for two out of every three dollars in product revenues; however, the static RAM approach will gain ground.
MEPTEC Luncheon Report
SAN JOSE, Calif. — Lee Smith, director of business development at Tessera, discussed 3-D packaging solutions at MEPTEC's January luncheon. Smith emphasized two applications, mobile handsets and memory modules for servers. Stacking of die, CSPs or both is needed to achieve the IC connection density required for products in the near future. Flash memory capacity has increased seven-fold in the past five years, and packaging companies currently provide CSPs containing up to four stacked die to accommodate these high-density memory chips. According to Smith, die stacking is reaching limitations as the number of stacked die increases and the cost of known good die exceeds that of a packaged device.
Tessera presented two solutions for stacking CSPs: a fold-over package using a flexible polyimide substrate and a "ball stack" using Tessera's µBGA technology. The folded package is best for combining different types of die from various manufacturers within the same system. The higher-yielding die (memory) and lower-yielding die (logic) are packaged and tested separately and then stacked during board-level assembly. This solution simplifies package-level testing and increases final package yield. Allowing die from different vendors to be packaged separately eliminates the confidentiality concerns that would exist if competitor's die were placed in the same package. Solder joint reliability within the stack currently is being evaluated with board-level temperature cycling and drop tests.
The ball stacks are used primarily for memory modules operating above 400 MHz, for which conventional TSOP packaging requires too much space. Various types of memory can be packaged and tested individually, then combined within a single stack up to eight layers high.
Former Maxtor CEO Joins Solectron
Milipitas, Calif. — Michael R. Cannon has been named president and CEO of Solectron Corp. He succeeds Koichi Nishimura, who announced his intention to retire. Cannon also was elected to the Solectron board. He joins Solectron from Maxtor Corp., where he was president, CEO and director of a leading global supplier of hard disk drive storage products and solutions.
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The board also elected William A. Hasler, the company's lead independent director, to succeed Nishimura as chairman of the board. Hasler, a Solectron director since 1998, is co-CEO of Aphton Corp., an international biotechnology firm.
Synopsys Scientist Elected IEEE Fellow
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MOUNTAIN VIEW, Calif. — Rohit Kapur, Ph.D., principal engineer at Synopsys Inc. and IEEE group chair for the IEEE Core Test Language (CTL) standard, IEEE P1450.6, was named a Fellow by the IEEE Board of Directors at its November 2002 meeting. Kapur was recognized for his outstanding contributions to the field of IC test technology.
Formerly with Viewlogic, Kapur joined Synopsys in 1997. As principal engineer, Kapur is responsible for working closely with the product development team to design new technologies for IC design and test.
BP Microsystems Opens China Office
HOUSTON — BP Microsystems opened an office in Hong Kong to increase the company's presence and sales in this important Asian market.
The new office will be run by Antoine Tran, and will provide sales and marketing support for China. Service and support for China will continue to be provided by BP Microsystems's global network of distributors.
Tran comes to BPM from within the electronics industry and will take charge of the China office as the business development manager for China.
President of SEMI China Named
SAN JOSE, Calif. — Semiconductor Equipment and Materials International (SEMI) promoted Yee-Ming Ting to the position of president, SEMI China.
Ting, who joined SEMI in 2002 and served as vice president and general manager of SEMI China, oversees all operations for the industry association in China. He continues to report to SEMI President and CEO Stanley T. Myers and is in charge of the association's relationships with its members as well as industry, government and academia in the region. Ting continues to operate from the SEMI office in Beijing.
August Enters Semiconductor Agreement
MINNEAPOLIS — August Technology entered into a development agreement with a top 10 semiconductor manufacturer.
The collaboration will move August Technology's inspection technologies into new crucial areas of the wafer fabrication process by leveraging the company's extensive capabilities in rapid automated defect inspection with the partner's leading-edge device manufacturing expertise.
August Technology's automated inspection solutions provide critical product and process-enhancing information, which enable microelectronics device manufacturers to drive down costs and time to market. According to Gartner Dataquest's "Midyear 2002 Semiconductor Manufacturing Market: Wafer Fab Equipment" report, the overall process control market is estimated to grow by 25 percent annually, nearly doubling in size to $5.40 billion in 2005 from $2.76 billion in 2002.
ASAT Appoints Senior VP, GM
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HONG KONG and FREMONT, Calif. — ASAT Holdings Ltd. and ASAT Inc. appointed Charles F. L. Ward senior vice president and general manager of ASAT Inc.
Reporting to Harry R. Rozakis, CEO of ASAT Holdings Ltd., Ward will oversee ASAT's U.S. operations.
Ward brings more than 15 years of business and management experience to ASAT and has an established track record in providing profit and results.
SUSS Introduces WLP Lithography Technologies
MUNICH, Germany — SUSS MicroTec introduced four technologies in conjunction with their lithography solutions for WLP.
The combination of Mask Protection Technology (MPT), Contrast Enhancement Material (CEM), Temperature Controlled Exposure Chuck (Thermalign) and Large Clearfield Movement (LCFM) enhances the performance of mask aligner technology beyond today's requirements for WLP and wafer-level redistribution.
MPT originally was developed and licensed by Motorola and has been successfully applied to mask aligners for contact exposure. Working with Kulicke & Soffa Flip Chip Unit, one of SUSS' strategic customers, the company has demonstrated for the first time that there are significant advantages for proximity exposure used for packaging applications.
CEM has been available to the industry for many years, mostly used in front-end IC manufacturing applications. In a joint effort with ShinEtsu MicroSi, SUSS was able to qualify the technology specifically for WLP requirements.
The Thermalign chuck is a hardware option for SUSS aligners and can be upgraded on existing systems. .
The SUSS LCFM option allows the user to "move the mask out of the way" while aligning the wafer.