Evolution of Wafer-level Packaging
07/01/2004
BY PETER ELENIUS
Sandia National Laboratories and Fujitsu conceived the wafer-level package (WLP) in the mid 1990s. Flip Chip Technologies (now FlipChip International) brought the first commercially successful WLP to production in 1998. One popular and useful definition of a WLP is that it is an IC package completely fabricated at the wafer level and assembled with standard SMT. WLP technology has evolved over the past decade from a nascent technology to one that enables many classes of devices and some OEM products. Significant reductions in device form factor and cost have been achieved, while at the same time increasing the electrical performance.
The first WLP technologies introduced were available only from wafer bumping foundries. In 1996 and 1997, when the bump foundries were developing the first commercial WLPs, no companies were designing ICs with 0.5- to 0.8-mm I/O array pitches. The WLP had to provide redistribution capability to translate the standard wire bond pad I/O to an area array format. Most of the early WLP development focused on the requirements of flash and DRAM devices with large die sizes and moderate I/O counts. However, widespread market adoption of WLPs has not occurred for either flash or DRAM devices.
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Suppliers of integrated passive devices and analog ICs first recognized the potential of the WLP as an enabler of their products. Today, the range of products produced in WLPs includes power MOSFETs, EEPROMs, small logic devices, transient voltage suppressors and a number of other device families. All of these devices are small, with bump counts that range from 2 to a maximum of 36. The image below shows products typical of most WLPs produced. Cell phones consume more than 90 percent of all WLPs produced today. WLPs enable the small form factor and increased functions desired in modern cell phones.
Many WLP devices are optimized for a specific process technology. These devices are often designed and fabricated with bump pads in the correct location, creating a bump-on-I/O structure. This simplifies the process steps required to produce the WLP. Reducing the layer count is now feasible or, in many cases, the use of an electroless nickel and immersion gold for the under bump metallization is possible.
In the future, the use of WLPs will increase — not only in cell phones, but also in other portable products that have similar form factor requirements. The principle applications served will continue to be devices with low I/O counts and low I/O densities. A WLP is not the optimal package for high I/O density devices because of the limitations of the SMT assembly process and the wiring constraints of the board it is mounted to.
A possible opportunity for WLPs will be in the packaging of future DRAM devices. There are indications that higher-end DDR2 and DDR3 devices will need an improved interconnect, as compared to the wire-bonded ball grid arrays (BGAs) already introduced for DDR2. A WLP may meet the requirements for this improved interconnect, but numerous factors must be addressed. These factors include: I/O density, reliability, burn-in, assembly processes and cost to name a few. An important factor will be the I/O density over the life of a given DRAM size. While the I/O density can be relatively low at early IC process technology nodes, there is a high probability at the last one or two process nodes for each device generation that all of the I/O will not fit within the IC footprint. This may drive the preferred packaging solution to a flip chip or other technology.
The WLP has enabled a significant number of devices in the market that address the needs of the end customer. That end customer is primarily the cell phone industry, but the OEM customer and application base will expand as WLP technology becomes more pervasive. It is important to remember that a WLP is not the ultimate package for every device produced. The WLP is, however, the ultimate package when it meets the needs of both the device manufacturer and the OEM.
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PETER ELENIUS, managing partner, may be contacted at EG&G Technology Partners LLC, 1840 East Warner Road, A105, #249, Tempe, AZ 85284; (602) 332-8272; e-mail: [email protected].