3D: Is the Best Yet to Come?
09/01/2007
While 3D stacked die and stacked packages are growing at an estimated 20% per year, packaging competitors continually develop technical refinements. Meanwhile, as front-end based packaging moves towards production, both dominant technology and the packaging supply chain could be disrupted.
Current 3D Trends
Higher Die Stacks. Samsung announced stacking 16 NAND flash memory chips thinned to 30 μm and wire-bonded in a single 1.4-mm-thick package. Samsung’s earlier version stacked ten 45-μm die. The company also developed a laser-cutting technology to dice thin wafers. Reducing the inter-die adhesive layer thickness from 60 μm to 20 μm while maintaining the thin layer’s uniformity is significant.
Samsung’s thinner packaging will be applied to present commercial products, which generally stack 5 or fewer die, to accommodate continuing pressure for thinner multi-chip packages in cell phone and other hand-held applications.
Lower Package Stacks. Tessera developed a copper inter-package contact layer to reduce total stack height. The contacts are tapered copper micro-pillars with a height of 25 to 175 μm, base diameter of 65 to 375 μm, and tip diameter of 40 to 200 μm, resulting in lower height and either finer interconnect pitch or wider trace space than conventional CSP solder ball packaging. Tessera sees further applications in die-to-substrate and substrate-to-PCB assembly, as well as in package-on-package (PoP) stacking.
Faster Chip Stacks. Competing in a different parameter, Irvine Sensors announced a new method to increase the speed of stacked die. Conventional chip stacking with closely spaced bond wires introduces parasitics that substantially reduce high-speed performance. Irvine demonstrated stacking four 500 mHz DDR memory die with no degradation in speed, and is exploring commercial opportunities for their patented technique.
Possible Disruptive Developments
Through-silicon vias (TSV) eliminate bond wires in die stacks to shrink 3D packaging while improving high-speed performance. Recent announcements indicate TSV is moving out of the laboratory and into the factory. The open question is whether that factory will be a packaging house or a wafer fab.
Amkor Technology and IMEC, the independent research center located in Leuven, Belgium, commited to a two-year collaboration to develop cost-effective 3D packaging based upon wafer-level processing. Amkor, who pioneered low-cost, high-volume 3D packaging in 1998, claim industry leadership in 3D packaging of mixed signal and logic + memory devices. Amkor introduced its PoP 3D line in late 2004. By the end of 2006, this was the fastest growing line in Amkor history.
Over the last few years, IMEC has been steadily developing its “copper nails” approach to die stacking with TSV. The vias are copper-filled in the first metallization step of front-end wafer processing. The TSV terminate in copper posts raised a few microns above the back surface of the wafer. Interconnection to other die or to substrate metallization is by thermocompression bonding.
The joint IMEC-Amkor collaboration announcement specified “cost-effective” techniques, and Amkor stated their objective as “low-cost, state-of-the-art packaging solutions.” IMEC is also expanding its 3D activity to include design technology, to exploit novel 3D technologies while limiting integration costs. If these collaborators can jointly develop a low-cost front-end based technology, it could become a 3D leader.
Meanwhile, Taiwan Semiconductor (TSMC), a leading pure foundry wafer manufacturer, announced a $60 million investment to establish a 12" wafer level packaging (WLP) technology, with production capacity to meet projected future market demand. TSMC holds about a 50% market share of worldwide foundry revenues, and is the 10th largest overall wafer producer. TSMC has previously offered design, packaging, and test as a customer service, but much of its present wafer production goes to assembly houses. Moving WLP in-house could take business from current packaging customers.
Conclusion
Since the onset of wafer-level packaging, conventional wisdom has been that wafer suppliers would have a competitive advantage over packaging houses if packaging begins in the front end of the wafer line. The announced programs may initiate that long-predicted change. The result could be smaller, faster 3D packaging, delivered by wafer suppliers instead of packaging houses.
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George Riley, Ph.D., contributing editor, may be contacted at Flip Chips Dot Com, 210 Park Ave. #300, Worcester, MA 01609; 508-753-3572; E-mail:[email protected].