Issue

Driving around after a recent snowstorm in the Northeast U.S., and seeing how rapidly the roads are kept clear, got me thinking about socket contact cleaning.

The term “total cost of ownership” (TCO) has reached the point where it is a default catch-phrase for many business people.

The ECT-original Gemini Kelvin probe is a solution that makes reliable, true Kelvin contact for high-volume production test.

Setting the tone for the 9th annual BITS Workshop, March 9-12, Mesa, AZ, with a presentation entitled “Packaging & Assembly in Pursuit of Moore’s Law and Beyond”, keynoter Karl Johnson , Ph.D., V.P and senior fellow at the advanced packaging systems integration laboratory, Freescale Semiconductor, will address new challenges, trends in packaging and assembly, and some unique solutions including system-on-chip (SOC) , 3D, system-in-package (SiP) and wafer-level assembly.

Last night the weather changed direction as often as a teenage girl changes outfits on the first day of school.

Although most of the semiconductor industries’ greatest discoveries and inventions are the results of years of research and development at prestigious universities and research institutes, some of the best solutions out there were developed in the trenches, on the manufacturing floor.

Technical process innovations in wafer-level packaging (WLP) have increased due to higher functional density, critical device real estate, an increase in market entry barriers, and stronger process integration capabilities.

Driving forces for 3D integration have been clearly identified and through-wafer via (TSV) technology continues to move closer to high volume production.

Image sensor module testing does not need to be a confusing collection of acronyms, test equipment, and charts.

The advent of pulsed lasers with short wavelength, focusable output, and high power levels presents opportunities for tool builders and end-users in package singulation.

As ICs move toward high clock speeds with pin densities reaching 0.5-mm pitch and pin counts over 1000, packaging for such devices must feature finer interconnections and improved electrical and mechanical performance.

Devices on sophisticated flip chip wafers have greater than 10,000 bumps, and are approaching upwards of 17,000 bumps.