Table of Contents
Solid State Technology
Year 2008 Issue 2
![](https://sst.semiconductor-digest.com/wp-content/uploads/magazines/print/issues/ap172_cover.jpg) | DEPARTMENTS
Editorial Board Snowstorms and Sockets
Driving around after a recent snowstorm in the Northeast U.S., and seeing how rapidly the roads are kept clear, got me thinking about socket contact cleaning.
Industry Voices The Total Solutions PartnerVanity or Value Proposition?
The term “total cost of ownership” (TCO) has reached the point where it is a default catch-phrase for many business people.
Bits Workshop Product Sh Product Showcase
The ECT-original Gemini Kelvin probe is a solution that makes reliable, true Kelvin contact for high-volume production test.
In The News IN THE NEWS
Setting the tone for the 9th annual BITS Workshop, March 9-12, Mesa, AZ, with a presentation entitled “Packaging & Assembly in Pursuit of Moore’s Law and Beyond”, keynoter Karl Johnson , Ph.D., V.P and senior fellow at the advanced packaging systems integration laboratory, Freescale Semiconductor, will address new challenges, trends in packaging and assembly, and some unique solutions including system-on-chip (SOC) , 3D, system-in-package (SiP) and wafer-level assembly.
Editorial Freaky March
Last night the weather changed direction as often as a teenage girl changes outfits on the first day of school.
Advanced Packaging Road Brown Bag Engineers
Although most of the semiconductor industries’ greatest discoveries and inventions are the results of years of research and development at prestigious universities and research institutes, some of the best solutions out there were developed in the trenches, on the manufacturing floor.
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FEATURES
The Back End Process Process Equipment for Next-generation WLP Technologies
Technical process innovations in wafer-level packaging (WLP) have increased due to higher functional density, critical device real estate, an increase in market entry barriers, and stronger process integration capabilities.
Inside 3d Packaging Achieving High Aspect Ratio TSVs
Driving forces for 3D integration have been clearly identified and through-wafer via (TSV) technology continues to move closer to high volume production.
Inspection Amp Test Prac INSPECTION & TEST: Practical Issues in Image Sensor Module Testing
Image sensor module testing does not need to be a confusing collection of acronyms, test equipment, and charts.
Package Singulation Opti PACKAGE SINGULATION: Options in Laser Singulation
The advent of pulsed lasers with short wavelength, focusable output, and high power levels presents opportunities for tool builders and end-users in package singulation.
Sockets Ic Package Drive SOCKETS: IC Package Drives Contact Technology Innovation
As ICs move toward high clock speeds with pin densities reaching 0.5-mm pitch and pin counts over 1000, packaging for such devices must feature finer interconnections and improved electrical and mechanical performance.
Cover Story Stress-free Wafer Probing
Devices on sophisticated flip chip wafers have greater than 10,000 bumps, and are approaching upwards of 17,000 bumps.
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