Intelligent vehicle systems, particularly for autonomous self-driving applications, must be able to handle many different types of data – and a lot of it – very quickly. 3D hetero-integration technology opens up the possibility to assemble various functional blocks such as processors, memory, sensors, logic, analog, photonic, and power ICs into one stacked chip.

Tohoku University researchers continue to drive the state-of-the-art in this work. Having previously developed a 3D stacking technique for high-speed image sensors, they will take things further by detailing at the IEDM how they fabricated four stacked processors next to two stacked cache memories on a silicon interposer wafer, using reconfigured multichip-on-wafer 3D integration and backside through-silicon-via (TSV) technologies. They successfully evaluated and will discuss the essential requirements for this work, such as boundary scan, built-in self-test and self-repair functions in the stacked chips.

The images above are X-ray CT scans of TSV arrays in the four-layer stacked multicore processor chip (left) and the two-layer stacked cache memory chip (right).

(Paper #28.6, “Highly Dependable 3-D Stacked Multicore Processor System Module Fabricated Using Reconfigured Multichip-on-Wafer 3-D Integration Technology,” K.-W. Lee et al, Tohoku University)

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