By Ed Korczynski, Senior Technical Editor, SST/SemiMD
With anticipated economic limits to the continuation of Moore’s Law now on the horizon, it seems that moving into the 3rd dimension (3D) by stacking multiple layers of integrated circuits (IC) will be the ultimate expression of CMOS technology. Whether stacking heterogeneous chips using through-silicon vias (TSV), or monolithic approaches to forming multiple active IC layers on a single silicon substrate, 3D ICs should be both smaller and faster compared to functionally equivalent 2D chips and packages.
However, 3D ICs will likely always cost more than doing it in 2D, due to more step being needed in manufacturing. A recent variation of 2D IC packaging with some of the benefits of 3D is the use of silicon interposers containing TSV.
Current state-of-the-art electronic design automation (EDA) tools exist to handle complex IC systems, and can therefore handle complex 3D designs as long as the software has the proper inputs from a foundry’s Process-Design Kit. Figure 1 shows the verification flow for a multi-chip system using the “3DSTACK” capability within Mentor Graphics’ Calibre platform. Leading IC foundries GlobalFoundries and TSMC as well as 3D IC specialty foundry Tezzaron have all qualified 3DSTACK for their 2.5D and 3D design verifications.
FIGURE 1: “3DSTACK” functionality integrates with existing 2D Design Rule Check (DRC) modules within the Calibre platform. (Source: Mentor Graphics).
EDA tools have evolved in complexity such that Design-For-Test (DFT) methodologies and technologies now exist to tackle 3D ICs. Steve Pateras, product marketing director, DFT, Design to Silicon Division of Mentor Graphics advised, “If you’re stacking multiple die together, you need to work with known good die. The ROI basically changes for stacking, such that you need to get into a different regime of test.” In a die stack we have to think about not just known good die, but die known to be good after they are stacked, too. The latter condition mandates standards for DfT to allow test signals to flow between layers.
The IEEE 1838 working group on 3D interface standards is intended for heterogeneous integration, allowing for different IC process technologies, design set-ups, test, and design-for-test approaches. The standard defines test access features that enable the transportation of test stimuli and responses for both a target die and its inter-die connections.
Figure 2 shows the extra die interfaces that must be physically verified within a 3D IC system stack. Die interfaces can be mis-aligned due to translation or rotation during assembly, and with die from different fabs at different geometries it can be non-trivial to ensure that the rights pins are connected.
FIGURE 2: Schematic cross-section of a 3D IC system showing the die interfaces that require new Physical Verification (PV) checks. (Source: Mentor Graphics).
3D memory stacks are somewhat in their own category since they are primarily designed and manufactured by IDMs, though often with a logic layer on the bottom they are mostly homogenous, and since memory usually runs cooler than logic they generally have no cooling issues. For these reasons 3D memory stacks using wire-bonds have been in volume production for years, Micron leads the development of the Hybrid Memory Cube using TSV, and Samsung leads in growing multiple memory layers on a single silicon chip.
Future Demand for 3D Logic
So far, the only known commercial logic chips shipping with TSV are the Xilinx Virtex-7 product, where four 28nm node FPGAs (as reported by Phil Garrou in 2011 in his IFTLE blog) are connected to a silicon interposer. Xilinx has shown that much of the motivation for using 2.5D packaging was to improve yield when working with the maximum number of logic gates in the smallest available process node, and when foundry yields improve with learnings for a given node we would expect that the FPGA would be made using a single-chip 2D solution.
It appears that 2.5D is not so much a stepping-stone to 3D, as it is a clever variant on established 2D advanced packaging options. Silicon interposers with TSV offer certain advantages for integration of high-speed logic in 2D, but due to relatively greater cost compared to other WLP methods will likely only be used for high-margin parts like the Virtex-7. Also, Out-Sourced Assembly and Test (OSAT) companies have been offering both “fan-out” and “fan-in” wafer-level packaging (WLP) options, and heterogeneous integration can certainly be done using these approaches. “We have customers planning on using interposers, but they’re planning on lower-cost substrates,” commented Michael Buehler-Garcia, senior marketing director for Calibre, Design to Silicon Division of Mentor Graphics.
If high volume CMOS logic will always be most cost-effectively integrated in a single 2D slice of silicon, and heterogeneous integration of CMOS can be done in 2D using FD-SOI substrates, then what remains as the demand driver for future 3D logic stacks? What logic products require heterogeneous integration for basic functionality, would be band-width-limited by 2D packages, and also are anticipated to be shipped in sufficiently high-volume to allow for amortization of the integration costs?
Several vendor have recently launched 100G C form-factor pluggable (CFP) modules to increase speeds while reducing costs in communicating between data servers. ClariPhy produces a CFP SoC using a 28nm CMOS process that is packaged with laser diode chips from Sumitomo Electric Industries’ (SEI). “By combining ClariPhy’s SoC with SEI’s world class indium phosphide optics technology and deep experience in volume manufacturing of pluggable optical modules, we will deliver the benefits of coherent technology to metro and datacenter networks,” said Nobu Kuwata, general manager of the Technology and Marketing Department of Sumitomo Electric Device Innovations (SEDI). “We will provide first samples of our 100G coherent CFP next quarter.”
Even greater cost and power savings could derive from a revolution in the interconnections used not just between servers but inside the server farms that provide the ubiquitous “cloud computing” we are all coming to enjoy. “It’s still a couple of years out, but we’re doing research on DARPA projects now,” says Buehler-Garcia in reference to work Mentor Graphics is doing to bring the automation of its Calibre platform to this application space.
The EDA industry’s ability to handle system-on-chip (SoC) and system-in-package (SiP) layouts means that the differences between designing for 2D, 2.5D, and 3D logic should be minimal. “We don’t charge extra for 3D,” explained Buehler-Garcia, “it’s already part of the deal.” ‑E.K.
This article originally appeared on SemiMD, part of the Solid State Technology network