Defects that aren’t detected inline cost fabs the most. 

By DAVID W. PRICE and DOUGLAS G. SUTHERLAND, KLA-Tencor, Milpitas, CA

Defect inspection tools can be expensive. But regardless of the cost of the inspection tool needed to find a defect, the fab is almost always better off financially if it can find and fix that defect inline versus at the end of line (e.g., electrical test and failure analysis). Here, we are referring to the term defect in a general sense—the same concepts also apply to metrology measurements.

The third fundamental truth of process control for the semiconductor IC industry is:

The most expensive defect is the one that wasn’t detected inline.

FIGURE 1A (top) shows an imaginary SPC chart for a factory experiencing a baseline shift in defectivity (an excursion) beginning at Lot #300. FIGURE 1B (bottom) shows the same scenario except the fab has an effective inline monitor at the point of the excursion. In this case, the excursion is quickly identified and the offending process tool is taken offline for process tuning or maintenance. The excursion is contained and relatively few lots are impacted by the resulting yield loss.

FIGURE 1. It is always better to find and fix problems inline versus at the end of line. 1a. Problem identification and correction does not occur until bad wafers reach end-of-line test. 1b. Problem identification and correction occurs immediately.

The difference between these two scenarios is that in the top chart, the fab is unable to detect the excursion inline so the baseline shift continues unabated until the first affected lots hit end of line test. For a foundry process with a 60-day cycle time, this delay could easily exceed 20 days.

In our experience working with IC manufacturers, the majority of financial impact does not come from large excursions that cause significant yield loss to every affected wafer—those problems are usually identified and rectified very early on. Rather, the largest losses usually come from small excursions that are difficult to detect. They cause relatively low levels of yield loss but persist for prolonged periods of time. It is not uncommon to see thousands or even tens of thousands of wafers exposed to these low level excursions.

The culprit is nearly always a process control capability issue that can be traced back to one or more possible problems. The following list is not meant to be exhaustive, but is instead, representative of the most common causes:

FIGURE 2. Cost vs. mean time to detection (MTTD) of finding a defect inline. The curves are drawn for 4 different wafer costs in a fab with 100k WSPM. It is assumed that the excursion takes place at a single step in the process and happens once per year to each of the process tools at that step. The yield loss is assumed to be 20% during the excursion.

• Insufficient number of inspection points to allow effective isolation of the defect source.
• Failing to use a sensitive enough inspection tool or recipe (pixel size is too large, wrong wavelength,
• etc.)
• Inspection area of wafer is too low.
• Review sample size is too small.

Often, the original inspection strategy was carefully designed, but as time passed, changes were made to reduce costs. As new sources of noise are introduced in the SPC chart, the fab becomes less sensitive to small excursions.

FIGURE 2 shows the economic impact to the fab for the two scenarios shown by the SPC chart in FIGURE 1. Imagine an excursion which results in a net 25 percent yield loss (e.g., one out of four wafers must be scrapped). Finding that excursion at end-of-line (+30 days) versus inline (greater than one day) would amount to a staggering $21 million loss per occurrence for an average size run rate of 25k wafer starts per month. Given that this value only repre- sents the cost of re-manufacturing the scrapped wafers it could actually be a conservative estimate. The true cost could easily be double that amount for a fab that is running at the limit of their capacity since it would directly impact revenue.

Even if the situation requires the use of a relatively expensive inspection tool to find, monitor and resolve the problem, it is nearly always in the factory’s best interest to do so. One of the implications of this truth is that if an important defect type can only be detected by a certain inspection tool, then that inspection tool is almost always the most cost-effective solution for that layer. Rather than modifying process control strategies to save costs, it is nearly always in the factory’s best interest to maintain capable, inline process control strategies that prevent the financial impact of ‘the most expensive defect.’

Author’s Note: This is the third in a series of 10 installments that explore fundamental truths about process control—defect inspection and metrology—for the semiconductor industry. Each article introduces one of the 10 fundamental truths and highlights their implications.

Read more Process Watch:

Process Watch: Fab managers don’t like surprises

Process Watch: The 10 fundamental truths of process control for the semiconductor IC industry

Process Watch: Exploring the dark side

“The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”