EV Group (EVG), a supplier of wafer-bonding, lithography/nanoimprint lithography (NIL), metrology, photoresist coating, cleaning and inspection equipment, today announced its participation in the 3D integration consortium of IRT Nanoelec, which is headed by CEA-Leti. EVG joins Leti, STMicroelectronics and Mentor Graphics to develop advanced 3D wafer-to-wafer bonding technologies. SET also joined recently the consortium.
Based in Grenoble, France, IRT Nanoelec is an R&D center focused on information and communication technologies (ICT) using micro- and nanoelectronics. 3D integration is one of its core programs.
The 3D integration program was launched in 2012. It brings together, under a single roof, expertise and equipment addressing the entire 3D integration value chain: technology, circuit architecture, EDA tools, packaging and test. Mentor Graphics (EDA), ST (foundry) and Leti are the founding members of the consortium.
“The development of permanent bonding equipment and processes geared towards high-volume manufacturing of 3D stacked devices has been a focus area for EVG for more than 15 years. We are excited about the opportunities that result from joining forces with CEA-Leti, STMicroelectronics and Mentor Graphics to further develop and prove our solutions for advanced 3D technologies, such as 3D partitioning and advanced 3D imaging sensors,” said Markus Wimplinger, corporate technology development and IP director. “Being able to verify and further optimize bonding technologies with the most advanced product designs and in a leading-edge fab environment is critical for further progressing our technology development.”
Séverine Chéramy, director of the 3D integration program of IRT Nanoelec, said the consortium expects to achieve an interconnection pitch of about 1µm.
“The work with EVG, in the frame of IRT Nanoelec, will undoubtedly add value to the current program, because wafer-to-wafer stacking using direct Cu-to-Cu bonding is key for advanced 3D technologies, specifically for imaging application and 3D partitioning,” she said. “EVG’s knowledge on bonding will leverage the process expertise of the original members. The participation of EVG in the consortium will create new opportunities and optimized and cost-effective solutions for 3D IC devices.”
IRT Nanoelec previously announced that SET, Smart Equipment Technology, joined a consortium project to help develop advanced 3D die-to-wafer stacking technologies, using direct copper-to-copper bonding.
IRT-Nanoelec Research Technological Institute (IRT), headed by CEA-Leti, conducts research and development in the field of information and communication technologies (ICT) and, specifically, micro- and nanoelectronics. Based in Grenoble, France, IRT Nanoelec leverages the area’s proven innovation ecosystem to create the technologies that will power the nanoelectronics of tomorrow, drive new product development and inspire new applications – like the Internet of Things – for existing technologies. The R&D conducted at IRT Nanoelec provides early insight into how emerging technologies such as 3D integration and silicon photonics will affect integrated circuits.