Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced new capabilities that complete its holistic, integrated design flow for TSMC’s advanced wafer-level Integrated Fan-Out (InFO) packaging technology. Additionally, Cadence has unveiled enhancements for TSMC’s chip-on-wafer-on-substrate (CoWoS) advanced packaging technology. The complete InFO flow and enhanced CoWoS design methodologies enable design teams to efficiently complete the development process, from planning to analysis across multiple dies.

Completed InFO Design Flow

The Cadence^® tools that have been enhanced to complete the TSMC InFO flow include the Quantus™ QRC Extraction Solution, Physical Verification System (PVS), and the Voltus™ Sigrity™ Package Analysis solution. Additional tools in the flow include OrbitIO™ Interconnect Designer, System-in-Package (SiP) Layout, Sigrity XtractIM™ technology, Tempus™Timing Signoff Solution, Sigrity PowerDC™ technology and Sigrity PowerSI^® 3D-EM Extraction Option. With the completion of the flow, system-on-chip (SoC) designers can now:

• Create virtual interface blocks and automate parasitic extraction, enabling package-level cross-die timing analysis: Cadence provides the first available platform that offers cross-die coupling extraction via the Quantus QRC Extraction Solution and PVS, enabling InFO designers to efficiently complete timing analysis with the Tempus Timing Signoff Solution at the package level.
• Perform power DC and root mean square (RMS) electromigration (EM) and signal EM analysis: The Voltus Sigrity Package Analysis solution provides an integrated platform for power analysis across multiple dies and InFO designs.

CoWoS Reference Flow Enhancements

Cadence has also developed enhancements to the TSMC CoWoS reference flow. The new capabilities within the CoWoS refence flow enable designers to perform:

• Integrated electromagnetic interference (EMI) analysis that enables analysis of the CoWoS system: Cadence is now offering an updated Sigrity EMI flow with automatic design merging, enabling integrated EMI analysis, as well as broadband-frequency-dependent S-parameter simulation, allowing for E/H-field analysis of the CoWoS system.
• Static/dynamic IR analysis from a single environment: Voltus IC Power Integrity Solution now allows designers to do static/dynamic IR analysis across die and silicon interposers concurrently, while also analyzing power EM (dynamic/static) and signal EM (peak/RMS/average) for both dies and interposers within a single tool environment.
• Correct cross-die interface alignment among dies and interposers: The PVS design rule checking (DRC) and layout versus schematic (LVS) capabilities provide cross-die DRC and power/signal connectivity checks, ensuring the cross-die interface has the correct alignment among the dies and interposers.
• Thermal analysis across the CoWoS package, allowing accurate thermal runway predictions and reduced EM pessimism: The Voltus IC Power Integrity Solution and Sigrity PowerDC technology enable designers to do layer-based thermal analysis across the CoWoS package, which includes automated power map generation for all die within the solution and layer-based temperature map generation.
• Parasitic extraction for silicon interposers, enabling timing and electrical analysis: The Quantus QRC Extraction Solution offers performance RC extraction, generating Standard Parasitic Exchange Format (SPEF) data for cross-die timing analysis. Additionally, Cadence Sigrity XcitePI^™ technology provides RCLK extraction for frequency domain, signal integrity and power integrity simulation.

“We see a strong demand from both mobile and high-performance computing customers wanting to quickly deploy systems based on TSMC’s advanced packaging technologies,” said Tom Beckley, senior vice president and general manager of the Custom IC & PCB Group at Cadence. “Through our close working relationship with TSMC, we have completed TSMC InFO design flow and enhanced TSMC CoWoS reference flow, enabling our mutual customers to further shorten design and verification cycle times so they can get to market faster.”

“The Cadence solution for InFO technology enables our customers to deliver designs with increased bandwidth within small form factors,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “With these enhancements, the integrated full-flow addresses the market need for faster design and verification cycles. Additionally, the new capabilities added to the Cadence solution for CoWoS supports our customers who want to utilize this holistic reference flow for advanced packaging projects.”