ArterisIP, the supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today announced it has joined the FDXcelerator Partner Program. This program enables SoC designers to integrate ArterisIP interconnect IP into their projects with the ability to accelerate the timing closure process for FDX-based designs. The partnership speeds the development of pioneering products in applications from automotive ADAS and machine learning to small IoT processors.

ArterisIP offerings participating in the FDXcelerator program include:

• The Ncore Cache Coherent Interconnect IP with Ncore Resilience Package, which has been chosen by the industry’s leading automotive ADAS, autonomous driving, and machine learning SoC vendors for its power, performance, and area advantages and ISO 26262 functional safety features.
• The FlexNoC Interconnect IP with FlexNoC Resilience Package, which is the backbone interconnect for most mobility and consumer electronics SoC designs where power consumption, performance, and cost are key design metrics.
• The PIANO Timing Closure Package, which assists back-end timing closure with technology that works earlier in the SoC design flow, thereby reducing schedule risk.

“The addition of ArterisIP to the FDXcelerator Partnership Program has already realized benefits with the implementation of an FD-SOI automotive ADAS multi-processor SoC with fellow FDXcelerator partner Dream Chip Technologies,” said Alain Mutricy, senior vice president of product management at GF. “ArterisIP’s commitment to GF’s FDX technology enables a scalable on-chip interconnect IP technology that will help our customers meet stringent automotive safety requirements.”

“GF’s FDXcelerator program plays an important role for ArterisIP, enabling us to gain access to FD-SOI technology process and design information to enable improved automation of our interconnect timing closure assistance technology,” said K. Charles Janac, President and CEO of ArterisIP. “Interconnect timing closure assistance is becoming imperative as technologies like FD-SOI shrink feature sizes and allow ever-increasing transistor and wire densities.”