Category Archives: 3D Integration

The semiconductor industry posted record results in 2017, with revenue exceeding US$400 billion. Overall demand for semiconductor devices was robust throughout the year, driven by the growing adoption of electronics components across all applications, with particular strength in the mobile and data center markets. Semiconductor growth in 2017 was led by the memory segment, with impressive revenue reaching US$126 billion. It represents an increase of over 60% year-over-year. Yole Développement (Yole) Memory Team forecasts the memory market to reach US$177 billion in 2018, with 40% growth.

Under this dynamic ecosystem, Yole and its partners System Plus Consulting and Knowmade, all parts of Yole Group of Companies, deeply scan the memory area. They propose today valuable memory services to deliver world class research, data and insight. Their aim is to ensure its clients are well-versed in all aspects of this competitive industry. Yole Group of Companies leverage decades of industry experience and expertise while partnering with its clients to make sure they are consistently well-informed on this pushy market.

Today two memory research services, DRAM Service and NAND Service have been developed by Yole Group of Companies. Full description of both services are available in a new dedicated Memory section on i-micronews.com. In addition, a selection of technology & market news are daily selected by Yole’s memory team and posted in this section.

Make sure to collect deep insights and significant analyses from leading industry experts, combining over 50-year experience in memory and semiconductor-related fields.

Both DRAM and NAND markets were in a state of undersupply throughout the year, leading to rising prices and record revenue and profitability for the memory suppliers. Demand was very strong, led by mobile and data center / SSD and augmented by emerging growth drivers including AI , IoT and automotive. Supply growth across both DRAM and NAND was constrained, due to a combination of limited wafer growth and technological challenges.

The current macro trends of AI and machine learning, mobility, and connectivity, are favorable to both the DRAM and NAND markets, and will likely result in Memory continuing to increase its share of the overall the semiconductor market.

“Understanding memory supply/demand dynamics and its relationship with pricing is vital to understanding the broader semiconductor market and all associated supply chains”, asserts Emilie Jolivet, Division Director, Semiconductor & Software at Yole.

The DRAM market is constantly evolving and changing. Yole Group is announcing a 22% CAGR for bit demand over the next five years.

“New Chinese suppliers threaten the current market balance, and emerging memory technologies are poised to cannibalize huge chunks of DRAM demand while the demand drivers of the past, including PCs and smartphones lose steam and no longer push industry demand,” comments .Mike Howards, VP of DRAM & Memory research within the Semiconductor & Software division at Yole.
In parallel, NAND market is expected to set another revenue record in 2018, before a flattish 2019. Therefore it continues to expand, with several consecutive quarters of record revenue and profitability for suppliers.

NAND’s competitive landscape remains incredibly dynamic. Samsung is prepping its first fab at its massive Pyeongtaek site; Intel is emerging as a stand-alone supplier with capacity in China; and the sale of Toshiba’s memory business to a consortium led by Bain Capital is finally happening. Meanwhile, a new entrant looms on the horizon: China’s Yangtze Memory Technologies Co. (YMTC), which threatens to disrupt the status-quo as well as multiple other Chinese projects.

“NAND demand remains robust, with strong growth for enterprise SSDs in data centers, increasing adoption of SSDs in laptop PCs, and continued content growth in smartphones and other mobile devices,” asserts Walt Coon, VP of NAND and Memory Research at Yole.“These segments will continue driving the bulk of NAND bit consumption, though several emerging trends are poised to augment future growth, including AI and VR adoption, automotive, and IoT,” he adds.

Memory Research Service from Yole, provides all data related to NAND/DRAM revenue per quarter, NAND/DRAM shipments, pricing per NAND/DRAM type, near and long-term revenue, market share per quarter, CAPEX per company, and a market demand/supply forecast. It also includes a complete analysis and details on the demand side, with a deep dive into client and enterprise SSD, data centers, mobile, automotive, graphics, PC, and more. Each Memory Research Service is composed of both products, the Quarterly Market Monitor and the Monthly Pricing Monitor.

During the next few weeks, Yole’s Memory Team will attend a selection of key trade shows and conferences to present the Memory Research Services. Make sure you will be there and ask for a meeting right now. Mike Howard and Walt Coon will for example be at SEMICON West mid-July and the Flash Memory Summit (Santa Clara, CA, North America – From August 6 to 9) in August. More information: Yole’s Agenda

At this week’s 2018 Symposia on VLSI Technology and Circuits, imec, the research and innovation hub in nanoelectronics and digital technology, will present a process flow for a complementary FET (CFET) device for nodes beyond N3. The proposed CFET can eventually outperform FinFETs and meet the N3 requirements for power and performance. It offers a potential area scaling of both standard cells (SDC) and memory SRAM cells by 50%.

The CFET is a further evolution of the vertically stacked gate all around nanowire transistor. Instead of stacking either n-type or p-type devices, it stacks both on top of each other. Imec’s proposed flow consists of stacking an n-type vertical sheet on a p-type fin. This choice exploits the FinFET process flow and benefits from the potential for strain engineering in the bottom pFET. Based on TCAD analysis, the proposed CFET can meet the N3 targets for power and performance, where it will outperform FinFETs. However, the dominant parasitic resistance of the deep vias needs to be reduced. This can be achieved by introducing advanced Middle of Line (MOL) contacts using e.g. ruthenium.

A design-technology co-optimization (DTCO) analysis reveals that the CFET device used in either an SDC or SRAM cell has the potential of 50% area reduction. The SDC area is mostly driven by accessing the transistor terminals. Consequently, the area gain using CFETs will not lie in the reduction of the active footprint, but rather in the considerable simplification of the transistor terminal access. By fully benefiting from the CFET architecture, it is possible to reduce the SDC to three routing tracks whereas the most advanced FinFET libraries today need six. For SRAM cells, the same area reduction is possible thanks to a new cross-coupling scheme that allows us to scale the cell height from T6 to T4.

“Given its excellent characteristics and scaling potential, the CFET device is an excellent contender for the new device architecture we need for nodes beyond N3, pushing the horizon for Moore’s Law farther out,” stated Julien Ryckaert, distinguished member of the technical staff at imec.”

These results will be presented on June 21 at the VLSI Technology Symposium, in session T13: FET performance and scaling. This research is performed in cooperation with equipment companies TEL Coventor and Lam Research and with imec’s key program partners including GlobalFoundries, Huawei, Intel, Micron, Qualcomm, Samsung, SK Hynix, Sony Semiconductor Solutions, TOSHIBA Memory, TSMC and Western Digital.

At this week’s 2018 Symposia on VLSI Technology and Circuits, imec, the research and innovation hub in nanoelectronics and digital technology presented considerable progress in enabling germanium nanowire pFET devices as a practical solution to extend scaling beyond the 5nm node. In a first paper, the research center unveiled an in-depth study of the electrical properties of strained germanium nanowire pFETs. A second paper presents the first demonstration of vertically-stacked gate-all-around highly-strained germanium nanowire pFETs.

“With a number of scaling boosters, the industry will be able to extend FinFET technology to the 7- or even 5nm node,” says An Steegen, EVP at imec’s Semiconductor Technology and Systems division. “Beyond, the gate-all-around (GAA) architecture appears as a practical solution since it reuses most of the FinFET process steps. But one important challenge of using lateral nanowires is the significant decrease of the channel cross-section compared to conventional FinFETs. To improve the drive per footprint, several nanowires have to be stacked, but this comes with a serious penalty of increased parasitic capacitance and resistance. A solution is to replace the silicon nanowires by a high-mobility channel material such as germanium (Ge), providing the necessary current boost per footprint”, adds Steegen, “These new studies show that solution is indeed feasible, reaching the cost, area and performance requirements for nodes beyond 5nm.”

The first study of high-performing strained Ge nanowire pFETs gives insight in the device performance these new devices may offer for high-end analog and high-performance digital solutions. One conclusion is that dedicated optimizations of key process steps make these devices a serious contender for the GAA technology. The second paper reports on Ge GAA FETs with single nanowires, achieving a performance that matches state-of-the-art SiGe and Ge FinFETs. Moreover, for the first time, strained p-type Ge GAA FETs with stacked nanowires were demonstrated on a 14/16nm platform. The GAA nanowire technology appears as a promising high-performance solution for future nodes, provided that the junctions are further optimized.

“These complimentary studies establish germanium GAA nanowire technology as a valid contender for the sustained scaling that will be required to fulfill the requirements for the data-driven IoT-era requiring huge computational power,” concludes Steegen.

These results will be presented on June 20 at the VLSI Technology Symposium, in session T8: Advanced FinFET and GAA. This research is performed in cooperation with imec’s key program partners including GlobalFoundries, Huawei, Intel, Micron, Qualcomm, Samsung, SK Hynix, Sony Semiconductor Solutions, TOSHIBA Memory, TSMC and Western Digital.

Micross, headquartered in Orlando, FL announced a new appointment within the company’s senior management team. Marshall (Mac) Blythe has joined Micross in the role of General Manager of Component Modification Services (CMS) located in Hatfield, PA.

Mac brings more than twenty-five years leadership experience in a variety of business development, operations & executive management roles to Micross. His career has been primarily focused in the Electronic Manufacturing Services industry, supporting customers across the Aerospace & Defense, Industrial, Healthcare and Communication sectors.

Mac comes to Micross from Creation Technologies where he served as Vice President, Business Development for Eastern North America. Previously, Mac was President of Accuspec Electronics (now 4Front Solutions) where he successfully led the team to accelerate revenue growth through improving the company’s operational effectiveness, manufacturing productivity and quality. Mac also spent over 12 years at Celestica, where he held key general management and senior sales leadership roles.

Mac earned his M.B.A. from the University of Chicago and holds a BA from UNC, Chapel Hill, NC.

“We are delighted to welcome Mac to the Micross team,” stated Richard Kingdon, CEO of Micross. “We are confident that Mac’s combination of leadership skills and industry experience will both drive Micross’ Component Modification business forward and enhance the effectiveness of our broader organization.”

Micross is the one-source, one-solution provider of Bare Die & Wafers, Advanced Interconnect Technology, Custom Packaging & Assembly, Component Modification Services, Electrical & Environmental Testing and Hi-Rel Products to manufacturers and users of semiconductor devices.

pSemi™ Corporation (formerly known as Peregrine Semiconductor), a Murata company focused on semiconductor integration, announces the availability of the PE29101 gallium nitride (GaN) field-effect transistor (FET) driver for solid-state light detection and ranging (LiDAR) systems. The PE29101 boasts the industry’s fastest rise times and a low minimum pulse width. This high-speed driver enables design engineers to extract the full performance and switching speed advantages from GaN transistors. In solid-state LiDAR systems, faster switching translates into improved resolution and accuracy in the LiDAR image.

“As GaN is proving its relevance in applications like solid-state LiDAR, design engineers are using pSemi high-speed drivers to maximize the fast switching benefits of GaN,” says Jim Cable, chief technology officer of pSemi. “Because of its rise and fall speed, the PE29101 enables the highest possible resolution imagery—something the industry needs for LiDAR to reach its fullest potential.”

LiDAR operates on the same principles as radar but instead uses pulsed lasers to precisely map surrounding areas. Traditionally used in high-resolution mapping, LiDAR is now used in advanced-driver assistance programs (ADAS) and is widely seen as an enabling technology to fully autonomous vehicles. Furthermore, solid-state LiDAR has emerged as the future leader in the commercialization of LiDAR systems, largely due to its affordability, reliability and compact size compared to mechanical sensors.

In LiDAR systems, the pulse laser’s switching speed and rise time directly impacts the measurement’s accuracy. To improve resolution, the current must switch as quickly as possible through the laser diode. GaN technology offers LiDAR systems superior resolution and a faster response time because of its very low input capacitance and its ability to switch significantly faster than metal-oxide semiconductor field-effect transistors (MOSFETs).

GaN FETs must be controlled by a very fast driver to maximize their fast-switching potential. Increasing the switching speed requires a driver with fast rise times and a low minimum output pulse width. The PE29101 offers these key performance specifications, enabling GaN technology to improve LiDAR resolution.

Winbond Electronics Corporation, a global supplier of semiconductor memory solutions, today announced the introduction of the W25N01JW, a high-performance, 1.8V Serial NAND Flash memory IC delivering a new high in data-transfer rates: 83MB/s via a Quad Serial Peripheral Interface (QSPI).

Winbond’s new high-performance Serial NAND technology also supports a two-chip dual quad interface which gives a maximum data transfer rate of 166MB/s.

This high-speed Read operation, some four times faster than existing serial NAND memory devices offer, means that the 1.8V W25N01JW chip can replace SPI NOR Flash memory in automotive applications such as data storage for instrument clusters or the center information displays (CIDs).

This is important for automotive OEMs because the adoption of more sophisticated graphics displays in the instrument cluster, and larger display sizes of 7 inches and above in the CID, is increasing system memory requirements to capacities of 1Gbit and higher. At these capacities, serial NAND Flash has a markedly lower unit cost than that of SPI NOR Flash, and occupies a smaller board area per megabit of storage capacity.

SPI NOR Flash has been the preferred memory technology in automotive displays for many years because of its high read speed, which supports the fast boot requirements of automotive user interfaces, and because of its high reliability and long data retention. By raising the data transfer rate of its serial NAND technology to 83MB/s – matching the read speed of automotive SPI NOR Flash – Winbond has ensured that the W25N01JW can support fast boot operation and the demanding requirements of sophisticated graphics applications.

The W25N01JW also meets strict automotive requirements for quality and reliability. Built with high-reliability single-level sell (SLC) memory technology, and implementing 1-bit error correction code (ECC) on all Read and Write operations, it complies with the endurance, retention and quality requirements of the AEC-Q100 standard and relevant JEDEC specifications.

The W25N01JW device operates from -40°C to 105°C and retains data for 10 years at 85°C after 1,000 program/erase cycles, whereas eMMC can only retain data for a fraction of that time under these conditions even when used in SLC mode, which are today widely used for data storage in the CIDs of high-end vehicles.

“Cars’ large and attractive displays need higher memory capacity, beyond the ‘sweet spot’ of SPI NOR Flash, which is good for up to 512Mbits,” said William Chen, deputy director of the Flash Product Marketing Division at Winbond. “For systems that require high-speed memory in capacities of 1Gbit or higher, Winbond’s high-performance Serial NAND Flash is the new best choice for automotive OEMs, offering a combination of lower unit cost, smaller size and excellent reliability and data retention.”

The W25N01JW is available for sampling today in a capacity of 1Gbit. A two-chip implementation in dual-quad I/O mode provides 2Gbits of memory capacity and a maximum data transfer rate of 166MB/s.

The chip is available in industrial grade and in an extended-temperature automotive grade version operating at up to 105°C. It is compatible with standard SPI NAND Flash protocols. It is housed in standard 8mm x 6mm WSON and TFBGA packages that are footprint-compatible with standard SPI NOR Flash products.

Ease of use and design re-use across frequencies have not traditionally been associated with RF power solutions — until now. Today, NXP Semiconductors N.V. (NASDAQ:NXPI), a developer of RF power, introduces two new power blocks that promise to become a new standard for years to come.

The simplicity of these new devices lies in the availability of laterally diffused metal oxide semiconductor (LDMOS) technology for RF transistors in ubiquitous TO-247 and TO-220 power packages, that come with well established assembly processes. This is augmented with the simultaneous availability of very compact reference circuits that can be reused from 1.8 Megahertz (MHz) to 250 MHz. This results in considerable savings, fast time to market and optimized supply chain for most High Frequency (HF) and Very High Frequency (VHF) power systems.

Removing Barrier to Entry for RF Power
NXP’s new RF solutions include the MRF101AN 100 watt (W) transistor that is housed in the TO-220 package, and the MRF300AN 300 W transistor that is housed in the TO-247 package. While current plastic packages for high power RF require a precise solder reflow process, these transistors can be assembled to a printed circuit board (PCB) using a standard through-hole technology, reducing costs. Heatsinking is also simplified since the transistors can be mounted vertically to a chassis, or in more creative and versatile ways such as under the PCB. This opens many options for the mechanical design, contributing to lower the Bill of Materials (BoM) and reduce time to market.

“RF Power is moving increasingly into new applications, where the requirements for ease of use, high performance and versatility are essential,” said Pierre Piel, senior director and general manager for multi-market RF power at NXP. “We continue our mission to ease the use of RF Power by delivering solutions that minimize design requirements, reduce time to market and simplify the supply chain for our customers.”

Flexibility Without Compromise on Performance
At 40.68 MHz, the MRF300AN outputs 330 W Continuous Wave (CW), with 28 decibels (dB) of gain and 79 percent efficiency. As part of NXP’s series of extremely rugged transistors, the family is designed for use in unforgiving industrial applications and can withstand 65:1 Voltage Standing Wave Ratio (VSWR).

This performance is supported by 2 x 3 inch (5.1 x 7.1 centimeters) power block reference designs that use cost-effective PCB material. With only a change of coils and discrete components, and no change to the PCB layout, the board can be adapted to support any other frequency from 1.8 to 250 MHz. This ensures quick design cycle for RF designers to develop power amplifiers that address new markets.

For even more flexibility, each transistor comes in two configurations. For example, the MRF101BN mirrors the pin-out of the MRF101AN, enabling a compact push-pull layout to address wideband applications without compromise on efficiency.

The MRF101AN and MRF300AN target Industrial, Scientific and Medical (ISM) applications as well as HF and VHF communications. A new market is also expected with switch-mode power supply, since this technology enables switching at higher frequencies than existing solutions, reducing the size of other components of the BoM. The devices are part of NXP’s Product Longevity Program guaranteeing availability for 15 years.

Availability
The MRF300AN is available now. The MRF101AN is currently sampling, with production expected in September 2018. Reference circuits for the MRF300AN are available for 27 MHz, 40.68 MHz, 81.36 MHz and 230 MHz. For pricing or additional information, please contact your local NXP sales office or approved distributor.

IEEE, the world’s largest technical professional organization dedicated to advancing technology for humanity, and the IEEE Electronics Packaging Society (EPS) today announced Dr. William Chen as the recipient of the 2018 IEEE Electronics Packaging Award. The IEEE Electronics Packaging Award and the society’s other annual awards were presented on 31 May in San Diego, California, at the 2018 IEEE Electronic Components and Technology Conference (ECTC), the society’s flagship event.

Dr. Chen is an IEEE Life Fellow and Fellow of ASE Group in Sunnyvale, California. He is a former president of the IEEE Components, Packaging and Manufacturing Technology (CPMT) Society, as which the IEEE EPS was formerly known, and a prominent leader in the packaging community since his early years at IBM. He was recognized for his pioneering contributions to electronic packaging—from research and development through industrialization—and for his leadership in strategic roadmapping efforts in heterogeneous integration. Dr. Chen has been instrumental in the industrialization of game-changing packaging technologies which enabled miniaturization, cost reduction and performance enhancements for today’s pervasive, all-powerful electronic devices. He has been previously recognized for his work in the field and was the recipient of the IEEE CPMT David Feldman Outstanding Contribution Award in 2010.

At the IEEE Electronic Components and Technology Conference, IEEE EPS also honored other packaging leaders and innovators driving the research, design and development of revolutionary electronic microsystem packaging and integration technology:

In addition, Annette Teng of Promex Industries Inc., Gilles Poupon of CEA-LETI in France and Yoshitaka Fukuoka of Worldwide Electronic Integrated Substrate Technology Inc. in Japan received the 2018 IEEE EPS Regional Contributions Awards.

“The electronics industry is experiencing tremendous expansion and revolutionary change, repositioning electronic packaging as a value creator and product differentiator for broad domains of the semiconductor industry. Our members are at the forefront of this transformation, driving innovation in microsystem packaging in key areas such as heterogeneous integration, 3D packaging and the IoT (Internet of Things),” said Avram Bar-Cohen, IEEE EPS president. “This ECTC EPS luncheon showcased their efforts and the outstanding leadership of William Chen, to strengthen and expand the society as the leading global authority on packaging and integration and to help define the future of the electronics industry.”

IEEE EPS (https://eps.ieee.org) represents current and future technologists in electronics packaging, spanning every nuance from earliest-stage research, through design and prototyping, to assembly and manufacturing, and ultimately to ensuring safe and reliable operation. IEEE EPS is also increasingly serving as a focal point for information transfer and collaboration for other IEEE societies, as technologists in those technology areas seek to derive value from microsystem packaging.

Synopsys, Inc. (Nasdaq: SNPS) today announced that it has collaborated with Toshiba Memory Corporation to accelerate the verification of Toshiba Memory Corporation’s BiCS FLASH™ vertically stacked three-dimensional (3D) flash memory. By working closely with Toshiba Memory Corporation, Synopsys introduced innovative simulation algorithms in its FineSim® Pro FastSPICE tool to address the increased design complexity of 3D NAND Flash memory. These new technologies improve simulation speed by an average of 2X, thereby reducing multi-day simulation runs to less than a day.

Compared to traditional Flash devices, 3D Flash devices have much larger memory arrays, more complex analog and programming circuits, and extensive power distribution network.  Additionally, due to the stacked memory array structure, 3D Flash designs must deal with increased coupling effects due to layout parasitic elements. This increased complexity results in multi-day simulation times when using existing circuit simulation technology. Through close collaboration with Toshiba Memory Corporation, the latest release of FineSim Pro FastSPICE delivers several key technologies specifically optimized for 3D Flash simulation, for efficient handling of massive array structures, large power distribution network, increased layout parasitic elements, and high-precision analog circuits.

“FineSim has been our signoff circuit simulator since early 2000. Our long collaboration with Synopsys has enabled us to develop best-in-class Flash memory products for a broad range of applications,” said Shigeo (Jeff) Ohshima, Technology Executive SSD Application Engineering of Toshiba Memory Corporation. “By working closely with Synopsys we’re able to deploy FineSim Pro for verification of our latest BiCS Flash memories and meet our stringent quality and reliability requirements.”

“Advanced flash memory designs require extensive circuit simulation to ensure design robustness, reliability, and cost competitiveness,” said Paul Lo, corporate vice president of Engineering in the Design Group at Synopsys. “Our team is committed to continuing our close collaboration with Toshiba Memory Corporation to deliver novel circuit simulation technologies to meet the challenging needs of simulating complex 3D NAND Flash memories and enable Super Chips with Synopsys™.”

Upon the proposal of ST’s new President & CEO Jean-Marc Chery, the Supervisory Board has approved the establishment of a newly formed Executive Committee, entrusted with the management of the Company and led by Mr. Chery as its Chairman.

The other members of ST’s Executive Committee are:

  • Orio Bellezza, President, Technology, Manufacturing and Quality
  • Marco Cassis, President, Sales, Marketing, Communications and
    Strategy Development
  • Claude Dardanne, President, Microcontrollers and Digital ICs Group
  • Lorenzo Grandi, President, Finance, Infrastructure and Services and Chief Financial Officer
  • Marco Monti, President, Automotive and Discrete Group
  • Georges Penalver, President, Human Resources and Corporate Social Responsibility
  • Steven Rose, President, Legal Counsel
  • Benedetto Vigna, President, Analog, MEMS and Sensors Group.

“ST’s new Executive Committee is a team of strong and experienced semiconductor industry leaders. Our first priority is to deliver on our 2018 business and financial objectives and continue on our path of sustainable and profitable growth. Customers choose ST because we are able to bring them innovation in technology and products. We will keep pushing in this direction, with a focus on fast time-to-market and strong execution, to create value for customers and for all of our stakeholders.” said Jean-Marc Chery, President & CEO of STMicroelectronics.