Category Archives: 3D Integration

(July 8, 2009) GARCHING and MUNICH, Germany &#151 SUSS MicroTec and Thin Materials, a semiconductor process development company, are cooperating on a temporary bonding solution to be used for challenging thin wafer handling technologies required for emerging 3D integration and packaging technologies. With this cooperation SUSS MicroTec extends its solution portfolio for temporary bonding and thin wafer handling.

The temporary bond material of Thin Materials is capable of handling wafer processing temperatures in excess of 250&#176C while being able to do a room temperature de-bond. This simplifies the debond process by eliminating a number of steps thus saving time and lowering device costs. The Thin Materials process runs on SUSS MicroTec’s production wafer bonder, XBC300, whose modularity and high process flexibility can easily be adapted for changing environments and processed material. The XBC300 temporary bond configurations are available for development and high volume needs.

“We have been working closely with SUSS MicroTec as one of the leading experts for 3D integration solutions,” states Franz Richter, Ph.D., CEO of Thin Materials AG, “We are looking forward to extending this partnership and jointly supply our customers with cutting-edge solutions.”

“Thin Materials’ technology for temporary bonding complements our process offering portfolio for 3D Integration and Packaging,” confirms Frank Averdung, president and CEO of SUSS MicroTec “Partnering with Thin Materials allows us to offer our customers a wide variety of temporary bonding technologies according to their specific needs.”

Together with its partners 3M, Disco, DuPont, NEXX Systems, Surface Technology Systems, and Thin Materials, SUSS MicroTec will host a TSV 3D Integration workshop introducing solutions for temporary bonding and thin wafer handling on July 15th during SEMICON West, San Francisco, CA. For more information, visit www.suss.com/company/events/thin_wafer_processing_workshop_2009.

by Debra Vogler, senior technical editor, Solid State Technology

June 29, 2009 – Alchimer recently announced it had enhanced its eG ViaCoat process — a wet deposition process for the copper seed metallization of through-silicon vias (TSVs) — such that end users can now use existing (dry) equipment.

Reliability test results — exclusively released to SST — are shown in the figures below.

One important enhancement was increasing the conductivity of the formulation, which allowed the process to work at lower voltage regimes that are typical of existing ECD equipment, explained Alchimer CEO, Steve Lerner. The enhancements also opened up the process window in terms of the power supply’s demand. Additionally, the replenishment solution was taken from a two-part solution to a single-part solution, making it simpler to maintain. The key here, he told SST, is the power supply — “Unless one is working with a highly resistive, difficult substrate, we’re compatible with existing equipment.”

The industry has evolved to thinner and thinner films by depositing targeted material, which is ionized and then falls onto a surface, Lerner observed. If the traditional dry technologies are applied to a 3D structure (e.g., a HAR TSV), generally, one accumulates a lot at the top (overburden), a little bit at the bottom depending on the aspect ratio, and very little on the sides. “With our wet approach, the application is uniform and conformal,” he noted; “that’s the fundamental difference between a dry deposition vs. an electrografted wet deposition.”

The company calculates that purchasing an ECD tool enabled by Alchimer’s technology* would cost “far less” than if a chipmaker were to buy a dry tool — pointing to advantages of being able to use a new 3D/TSV technology without having to give up existing (dry) equipment, and without having to go through a learning curve on new equipment — “or potentially scrapping new equipment because the designs weren’t optimized for the manner in which the products will evolve, thereby paying a heavy price on the learning curve,” Lerner added. “But if you eliminate the capital equipment purchase altogether, you have the best of both worlds.”

He also believes that there is plenty of underutilized dry equipment, and that the current economic climate is not the time for end users to buy when they are also on a learning curve with respect to TSV technology. Echoing what has surely become the everyday mantra of consumers and businesses alike, he told SST that the industry will need to learn to make do with less, and learn to extend the life of its assets. — D.V.

*Edited 7/2/2009: Changed to reflect that Alchimer does not actually make the tools, but provides technology for them.


ViaCoat reliability test results. (Source: Alchimer)

by Debra Vogler, senior technical editor, Solid State Technology

June 8, 2009 – As IMEC completed preparations for its 25th anniversary celebration, SST spoke with Luc Van den hove about the research center’s strategy and the keys to its success over the years. On June 2, Van den hove was named IMEC’s president & CEO.

Reflecting on key factors to IMEC’s success, Van den hove noted that one factor is the consortium’s neutrality. “We’re located in a small neutral country, and we’re not dominated by one company — we are truly neutral,” he explained. “We get support from the local government, but it never pressures us to work with a company, or give preferential treatment.” He noted the Belgian government’s position is that for IMEC to be the number one R&D provider, it has to go out and work with the best, wherever they are located, and “that has been a very important reason for our success.”

Van den hove also believes that IMEC’s R&D model is economical for its members because members share the costs (with several partners participating in a program), but the benefits are also shared, and this customer-focused responsiveness is a key performance criteria. “We have also built in enough flexibility so that for partners who want to do proprietary work, they do not have to share that,” said Van den hove. “We adapt our offering to what’s needed by each partner — it’s not a take it or leave it model — we try to bring value to each of the partners.”

IMEC will continue its path to aggressively scaled CMOS technology, focusing on 22nm today, as well as developing the modules and materials that will be needed for the 15/16nm nodes. “These activities will go on for at least the next 10 years,” said Van den hove, “and they will remain an important pillar of our strategy.” Besides memory technology’s need for aggressive scaling, logic technology will need new materials, particularly extreme high-mobility materials, and both technologies will need advanced lithography and 3D integration, he said.

The consortium’s advanced lithography program is focused on developing more cost-effective double-patterning immersion lithography and EUV. “The nice part about EUV is that you can work with much higher k factors, a regime where lithographers are used to working,” he explained. Recognizing that the major challenge with EUV is cost-of-ownership — and the source throughput in particular –Van den hove said that IMEC is still very optimistic about EUV, calling it “the only technology that shows strong potential for implementation for large volume manufacturing for sub-22nm technologies.”

The second pillar of IMEC’s strategy is the expansion of activities into fields that are not directly related to aggressive scaling technology, but which reuse the basic technology IMEC has been developing in its core CMOS program. Van den hove noted that the only way to continue to get out of a downturn is to invest in innovation. “Companies will have to do R&D in the most cost-effective way, and we believe we have set up a model that has been very successful to tackle those R&D challenges,” he said. “So we are setting up plans to continue where we are strong and expand into new areas such as biomedical — where silicon-based nanotechnology can essentially be reused — and photovoltaics (PV), as well as other areas, to secure our success in the future.” In just the past few days, aligned to its 25th anniversary celebrations, IMEC has followed through with two announcements along these themes:

  • A Neuroelectronics Research Flanders (NERF), a research initiative with Flanders’ life science institute VIB and the Leuven University, housed on the IMEC campus, supported by a €3M research grant from the Flemish Government for the first three years. Kicking off in October with a roadmap, NERF aims to examine the functional mapping of the brain, generate research methodologies and technologies for medical applications, such as diagnostics and treatment of disorders of the central and peripheral nervous system.
  • Joint work with Schott Solar, to explore and develop wafer-based bulk silicon solar cells: thinning the active layer from 150μm to 40μm, introducing alternative back-side dielectric stacks and interdigitated back-side contacts using a passivated emitter and rear local (PERL) back surface field, and exploring cell module integration and reliability. Epitaxial thin-film (<20μm) silicon solar cells on low-cost silicon carrier also will be explored.

Van den hove pointed out that the origin of IMEC’s PV research was work done at the Katholieke Universiteit (K.U.) Leuven — IMEC was a spin-off from there, and PV research was a major part of the work done by the university team that eventually formed IMEC. “In the ’80s and ’90s, IMEC’s PV program didn’t get much attention,” Van den hove noted, but during the last five years attention has increased. “We kept working on solar cell technology for 25 years, continuing to support the program started in the university.” Although the program investigates several routes to PV, it is focused primarily on crystalline silicon (c-Si) PV. “We believe it’s the most promising technology, one of the only technologies that has demonstrated solar cells with lifetimes greater than 20 years and high-efficiency cells.” Now, the challenge is to reduce their cost by more than a factor of 4 in the next 10-15 years, he said. “We have a roadmap to achieve this by reducing silicon consumption (by thinning down the silicon substrate) while maintaining or slightly improving the efficiency of the cells.” Cell efficiency improvements will be addressed by tackling the processing steps, i.e., adjusting diffusions and contact schemes, and generally optimizing the process itself.

The other important PV program at IMEC is organic solar cells, which Van den hove explained have the advantage of being made out of very thin films (the absorption coefficient of organic material is very high), but with the challenges of lower efficiency and limited lifetime that need to be addressed. He estimates that this longer-term R&D work will require about 10-15 years before it can be used for high-volume PV fabrication. In the short term, though, organic PV can be used for consumer applications that don’t require a 20-year lifetime, such as integrated into clothing, or on tents, or where you need flexibility of the material. “These could be nice niche applications in the shorter term for organic solar cells,” he pointed out.

Another major R&D effort at IMEC is in the area of biomedical applications in which nanoelectronics and nanotechnology are used. Examples include functionalized nanoparticles for molecular imaging and curing cancers. “There are also activities for brain/computer interface, such as neuron on chip,” said Van den hove — activities that SST highlighted back in 2005. Research includes measuring signals in neurons and stimulating neurons, “which we think will give us a better understanding of how the brain works,” he said — “and that can be done making devices based on silicon technology. So we are reusing technologies we developed in core CMOS for applications in the biomedical field.” — D.V.

(June 2, 2009) RESEARCH TRIANGLE PARK, NC &#151 The 2009 3D Architectures for Semiconductor Integration and Packaging Conference and Exhibition will bring together industry leaders to examine the practical and competitive landscape on the path to implementation of 3D integration and packaging technologies, December 9 through 11, 2009, in Burlingame, CA.

This conference series, coordinated by RTI International, offers a unique techno-business perspective of the emerging 3D chips commercial opportunity, combining technology with business, research findings with practical insights, to offer industry leaders the information needed to plan and move forward with confidence.

3-D integration and packaging represents a paradigm shift for the semiconductor industry, opening new pathways for advancement and industry growth. The 2009 conference will continue to provide this unique forum dedicated to serving the needs of the entire 3-D community, and will also feature expanded exhibit offerings.

“Industry experts around the world have come to view 3D chips as a key enabler to continued performance improvements and market growth for the semiconductor industry,” said Phil Garrou, conference co-chair. “The challenges inherent in continued scaling in 2D are simply too daunting and only offer incremental improvements in performance, and at higher cost. Industry players who understand the challenges and opportunities, and offer new solutions, will reap the rewards for many years to come.”

For more information, or to register for the 2009 3-D Architectures for Semiconductor Integration and Packaging Conference and Exhibition, visit techventure.rti.org.

The Applied Materials’ Charger UBM PVD system was designed for under-bump metallization (UBM), redistribution layer and CMOS image sensor applications. Its linear architecture is said to more than double the wafer output of other systems. In addition, its proprietary Isani wafer treatment technology allows the UBM system to process ten times more wafers between servicing.

Isani wafer treatment is said to minimizes defects on organic and high-stress films and extend process kit life by up to 10X, which lowers cost of consumables compared with traditional inductively coupled plasma sputter chambers. Select magnetron and PVD chamber design improvements fulfill exacting film deposition uniformity specifications for various metals used in UBM and RDL applications (e.g., Ti, TiW, Cu, and NiV).

The Charger system’s modular architecture features flexible configuration allowing for expansion from a compact three-chamber R&D configuration into a five-chamber, high-volume manufacturing system with minimal downtime. Applied Materials Santa Clara, CA; www.appliedmaterials.com

ECTC 2009 In Review


June 1, 2009

In a time when R&D is at the forefront of the industry, events like ECTC 2009, held May 27-29 in San Diego, become critical for showcasing research achievements, as well as providing venues for learning about the latest developments across the spectrum of device manufacturing. With 16 professional courses, 39 sessions of 6 papers each, two poster sessions, and the opportunity to mix it up with prestigious members of academia and research institutes, calling the event informative would be an understatement. As my current focus is in the area of 3D IC integration and 3D packaging, my radar was mostly tuned in there, and I spent most of my time interviewing experts in that market sector. However, I did pick up some interesting news from those involved in other areas of advanced packaging technologies.

In the wafer-level packaging (WLP) realm, I got a status update from Mike Thompson, Mikael Fredenberg, and Patrik M

(May 29, 2009) MINNEAPOLIS, MN &#151 Professor Rao Tummala will keynote the 6th Annual International Wafer-Level Packaging Conference (IWLPC), October 27–30, 2009 at the Santa Clara Marriott Hotel in Santa Clara, CA.

The SMTA and Chip Scale Review present the conference. Professor Tummala is a Distinguished and Endowed Chair Professor, and Founding Director of NSF ERC at Georgia Tech, the largest Academic Center in Microsystems pioneering system-on-package (SoP) vision, since 1994. Prior to joining Georgia Tech, he was an IBM Fellow, pioneering such major technologies as the first plasma flat panel display based on gas discharge, the first and next three generations of multichip packaging based on 35-layer alumina and 61-layer LTCC with copper and copper-polymer thin film, and materials for ink-jet printing and magnetic storage.

Prof. Tummala has published 426 technical papers, holds 74 patents and inventions; authored the first modem packaging reference book, Microelectronics Packaging Handbook (Van Nostrand, 1988), undergrad textbook, Fundamentals of Microsystems Packaging (McGraw Hill, 2001), and first book introducing the SoP technology. He is a Fellow of IEEE, IMAPS, and the American Ceramic Society, and member of the National Academy of Engineering in USA and in India. He was the President of both IEEE-CPMT and the IMAPS Societies.

Sponsored jointly by the SMTA and Chip Scale Review magazine, the annual IWLPC explores cutting edge topics in wafer-level packaging and IC/MEMS/MOEMS packaging, including 3D/Stacked/CSP/SiP/SoP and mixed technology packages.

For more information, visit www.iwlpc.com.

To read Professor Tummala’s recent articles for Advanced Packaging, click:
3D Technology and Beyond: 3D All Silicon System Module
The 3DASSM Consortium: An Industry/Academia Collaboration
and
SoC vs. MCM vs SiP vs. SoP

The MetaPULSE thin film measurement tool from Rudolph Technologies is optimized specifically for copper via fill in 3D IC applications, as well as copper damascene processes at 45nm through 22nm technology nodes and copper via fill in 3D IC applications. Copper thickness and overburden measurements are critical in optimizing the CMP process that follows deposition during through-silicon via (TSV) manufacturing. The new tool measures reportedly can measure 60-80 product wafers/hour with gauge-capable precision and reduced cost of ownership.

Unlike optical and x-ray techniques, the MetaPULSE measures film thickness using a time-resolved acoustic signal that can be used in active die in the absence of special underlying test pads. The high-reliability, green wavelength ultrafast laser is optimized for copper applications, delivering higher signal-to-noise ratios and measurement repeatability better than 0.3% at throughputs of 60-80 product wafers/hour, supporting high-volume production. The system’s 10

May 15, 2009 – New integration trends and disruptive packaging technologies, notably 3D TSVs, will cause major technical changes in the memory semiconductor sector, but ultimately pave the way for future growth, according to a recent report from Yole Développement.

DRAM memory historically has been driven by computing applications (e.g., PCs); NOR flash has been targeted to consumer and communications devices; and NAND memory most recently seen as promising for solid-state storage (consumer devices) and as a likely replacement for hard-disk drives.

Proliferation of wireless technology (smart-phones to mobile pocket-sized computing devices) has led to increased data connectivity and integration in the form of WAN, LAN, PAN, HD multimedia, etc., collectively driving demand for higher data capacities and better power efficiency. This “is stressing established architectures” and requires new interconnects, integration schemes, and packaging technologies — particularly 3D IC integration — to support higher-performance, power-sipping devices, notes Jérôme Baron, technology and market analyst at Yole, in a statement summarizing the new report.

3D integration will be a key new application space for memory growth even as the economic downturn slows adoption of through-silicon vias (TSV) in high-volume applications such as low-cost memory, according Baron. “We see concrete signs that this market is definitely taking off, with the first 3D integrated DRAM memories being shipped this year,” he said, estimating that ~20,000 wafers of DRAM memory with 3D TSV will be shipped by year’s end, and ramping production further in 2010. By 2013, the firm expects telecom and computing sectors to be driving more than 70% of the total volume for 3D TSV stacked memories.


3-D TSV memory wafer shipments per industry, 2013 forecast. (Source: Yole Développement)

Acknowledging that 3D integration with memory is a “hot topic” in the current challenging market/macroeconomic environment, given the investment to build a 3D infrastructure, Yole expects to see “precompetitive alliances and partnerships” — likely consisting of memory manufacturers, CMOS foundries, outsourced semiconductor assembly and test (OSAT) packaging houses, fabless IC players, and integrated device manufacturers (IDMs) — to help individual suppliers mitigate risk and accelerate production.

(May 8, 2009) LYON, France &#151 The memory semiconductor industry is about to go through a period of major technological changes as new integration trends and disruptive packaging technologies pave the way to the future growth of this industry, reports Yole D&#233veloppement. Yole’s recent study presents the end applications driving the use of 3D integrated memories and their key players. It also includes an overview of the memory packaging market, its forecasted evolutions with new applications and growth in flash and DRAM.

Historically, the DRAM memory market has been mostly driven by computing applications, while NOR Flash has been mainly deployed into consumer and communication devices, Yole states. More recently, NAND flash memory has emerged as the most promising solid state storage solution for current consumer devices and is showing as the best candidate for hard disk drive replacement in the near future.

Wireless is growing and enabling new market segments from smart-phones to mobile pocket computing devices. As a result, connectivity and integration have become major industry drivers. Demand for data is increasing everywhere: faster pipes, more pipes (WAN, LAN, PAN), HD multimedia, and others. Current complexity and concurrency require higher data capacity and improved power consumption, which is stress-ing established architectures. New interconnects, integration schemes, and packaging technologies are needed to support higher performance, breakthrough density and low-power-consumption devices. 3D IC integration is showing as a major solution path to tackle these challenges; memories will be key components in achieving this successful integration.

3D integration will open a new application space for memory market growth, ac-cording to Yole, which sees the economic downturn as a challenge to thru-silicon via (TSV) adoption in high-volume applications such as low-cost memory. “However, we see concrete signs that this market is definitely taking off, with the first 3D integrated DRAM memories being shipped this year. We estimate that about 20,000 wafers of DRAM memory will be shipped with 3D TSV by the end of 2009, with production moving forward to higher volumes in 2010,” asserted J&#233r&#244me Baron, technology and market analyst at Yole. By 2013, Yole expects that telecom and computing industries will drive more than 70% of the total volume for 3D TSV stacked memories.

3D integration with memories is a hot topic because of the challenging market conditions and the required investment to build 3D’s infrastructure. Pre-competitive alliances and partnerships may be necessary to drive the risk down while accelerating product adoption, Yole reports. Memory manufacturers, CMOS foundries, outsourced semiconductor assembly and test (OSAT) packaging houses, fabless IC players, and integrated device manufacturers (IDMs) are concerned and actively preparing for this ultimate integration.

Yole’s study addresses the end applications driving the use of 3D integrated memories in flash and DRAM; the key players doing it; how it will progress and ramp up; and the impact of the current economic turmoil application per application. It also includes data on the forecasted size of the 3D memory market and costs.

To support its investigations in this complex market, Yole is also distributing the “Memory LSI &#151 2008 Report” from Nikkei BP Consulting, a market research company based in Tokyo, Japan that has been focusing on the analysis of the key market metrics of the memory industry, based on strong interactions all the year with memory fabs worldwide. The two complementary reports are available separately or both in a bundle package.

For more information, e-mail [email protected]; www.yole.fr.