By Fran
Category Archives: 3D Integration
(September 24, 2008) SHAUMBURG, IL —SMT editor-in-chief Gail Flower chaired a panel comprising equipment supplier, laboratory, EMS provider, and consultant voices at IPC Midwest in Schaumburg, Ill. David Geiger, Flextronics International; Jacques Coderre, Unovis Solutions; Vern Solberg, STI – Madison; and Gene Dunn, Panasonic Factory Solutions of America spoke about emerging packaging technologies.
Solberg started off with a focus on miniaturization. Wireless handsets are a major driver, but many other sectors are looking to improve speed and performance through miniaturization. Wafer-level packaging (WLP) and chip on board (COB) attachment are helping this trend. Interestingly, Solberg notes, the layout of WLPs are standard pitches to PCB assembly, even though they are bare die flip chips. At the wafer level, they are redistributed to these standard pitches. Solberg also discussed the logistics of die stacking within a package (system-in-package — SiP) against package-on-package (PoP) stacking, which can be done prior to board assembly or as part of the SMT assembly process, stacking up to eight packages. With low-profile packages, larger stacks can be achieved.
Dunn examined die and chip miniaturization, blended with a look at thin-die manufacturing and packaging issues, such as stress defects, that can result. Thinner wafers and smaller die sizes are filling packages today. Six years ago, 1.0mm sized die were considered small. Dunn says that 0.15mm die are today’s small die. Boards also are getting thinner and smaller. Cell phones can be less than 10mm thick and still offer feature-rich user experiences, Dunn noted. Thinness — with die trending toward 25µm thickness — brings fragility to these end-products’ components. Embedded applications are driving thinner, smaller chips, like 0201s, into multiple applications. By 2010, Dunn expects to see up to 10 thinned die with thin ball pitches in a 3D package. New technologies like plasma stress relief after wafer backgrinding, and plasma dicing in the back-end process are helping packagers cope with thin die. EMS providers will need to consider board layout for bend possibilities, pick-and-place systems for the force they put on components, and reflow overheat concerns. Encapsulation material for packages with thin, small die must help prevent warpage that can stress and bend die. For pick-and-place, tact times can get longer as the pick head slows down on approach to apply less force to the tiny passive component body. For PoP assembly, dip vacuum and depth are considerations for pick-and-place. How do you inspect flux/paste dip coverage before stacking? These and other considerations bring together equipment and materials suppliers to tackle emerging packages from an EMS perspective.
Coderre presented “Assembly Evolution as Semiconductor and Circuit Board Converge,” looking at the collaboration and convergence of package technology with board-level interconnect. At his lab, Coderre helps companies develop advanced processes in both semiconductor and PCB assembly sectors. This can take the form of fast, SMT-style processes moving into the semiconductor fabs and SiP packaging houses; and integrating flip chip and SMT into one line with one reflow pass; and bringing packaging steps into the circuits assembler’s facility. Embedded devices in the PCB, die feeders on pick-and-place systems, and other examples prove this trend. Coderre also sees board density as now including cubic density, not just 2D board layout density. This is like building up a city that can’t expand its geographical limits — metros go underground (into the PCB) and buildings stretch taller (stacked and 3D packages). EMS assemblers now must consider interconnect reliability inside the board, not just solder joints formed in the SMT line. Embedded components also require higher placement accuracy to avoid defects.
Finally, Geiger talked about how EMS assemblers implement these new packages in their process. Communication with the supply chain is important for integrating these packages and maintaining high yields. Land patterns, special vias, thermal grounds,flux dips, etc., all need to be taken into account, along with reliability requirements. PoP cannot be successful without proper reflow preventing warpage. Packaging companies can work with the EMS provider, and OEM companies are out of the loop. Or, OEMs sometimes work with the packagers, and then tell the EMS provider to build a product a certain way. The best way to work together, Geiger said, is to get the packaging house, OEM, and EMS provider together so everyone understands why the design and manufacturing must be done in the way that it is. He pointed out that the EMS provider has to ask questions and learn new things to successfully manufacture with these new packages. Additional elements like underfill for fragile packages, drop testing for 3D package reliability verification, etc. will come into the process faster if the EMS facility, OEM, and packaging house are communicating and querying each other productively.
In response to market needs for 300mm process equipment capabilities to demonstrate 3D processes, SUSS MicroTec has introduced The XBC300. The XBC300 is designed for 3D integration and 3D packaging with through silicon vias (TSVs) and is ideal for the CMOS image sensor (CIS) early adopter market.
The XBC300 is tailored to cover all 3D requirements by different process modules allowing for a combination of capabilities in a small package. The tool performs a range of wafer bonding processes in a small footprint. That, combined with high throughput capabilities reportedly optimizes cost of ownership for CIS applications. Process capabilities include 3D stacking with Cu-Cu that have smaller than 10um vias, fusion bonds including low-temperature processing for submicron overlay accuracy, force parallelism and uniformity ensures polymer confinement, and hybrid bonding of metal interconnects dielectrically isolated with either deposited oxide layers or adhesives. SUSS MicroTec, Wafer Bonder Division, www.suss.com
Using 2D and 3D X-ray Techniques to Find and Confirm Manufacturing Defects in Fip Chip Devices
By Evstatin Krastev, Ph.D. Dage Precision Industries, a Nordson Company
The basic, straightforward design of a flip-chip device calls for the conductive bumps of the silicon chip to be placed directly on the interconnection points of a substrate or PCB. This format eliminates excessive packaging, which offers operational benefits at high frequencies with low parasitics in a high I/O density. At the same time, high-density flip-chip devices place a greater burden upon device inspection during both the device manufacture and subsequent processing onto a substrate or PCB.
Flip-Chip Trends
The overall use of flip chips is increasing due primarily to performance advantages in multi-functional handheld devices where typical pin counts are in the 200-700 I/O range. Because of they’re inherently higher I/O density, the use of flip-chip devices for applications other than mobile or handheld products is generally limited to applications of 1,000 I/O or greater. However, the rising cost of gold has increased the demand for flip chip versus gold wire bonding to a point where the crossover point has come down to 500 I/O for several applications.1
Common Defects
Flip chip defects can occur when devices are reflowed and can include cracks, head-in-pillow and/or interfacial voiding. Tilt angle capability, or oblique angle viewing, is very critical for identifying flip chip defects and can be very easily accomplished using a modern 2D X-ray inspection system. It is good to use tilt or oblique angles of 55 to 70° and rotate the x-ray detector at 0 to 360° around the examined joint.
A flip chip crack less than 1mil is challenging for any X-ray inspection systems to detect. The proper use of tilt and rotation angles together with the right X-ray parameters including kilo volts (kV) and power is of crucial importance in detecting cracks (Figure 1).
Head-in-pillow defects are the phenomena that can occur when incomplete wetting of the entire solder joint results in the solder paste coalescing separately from the solder ball or solder bump after reflow. Also considered an open joint, head-in-pillow defects typically occur more frequently with ball grid array (BGA) devices but can also occur with flip chips (Figure 2).
Head-in-pillow defects are difficult to detect with lower performance 2D X-ray systems, and may require destructive cross sectioning in order to identify and confirm this deficiency when they fail at in-circuit test and functional test. However head-in-pillow defects can be easily identified with off-axis X-ray viewing using modern 2D X-ray inspection systems without destroying the flip chip, substrate or PCB.
Detecting small cracks down to 1mil or finer, as well as head-in-pillow defects is a challenge but can be accomplished using modern 2D X-ray inspection systems. The tilt and rotation angles need to be adjusted carefully since the two angles are among the key factors playing a critical role in identifying small features.
3D Packages
With the continued emergence of subsystem integration, advanced 3D packages including flip chip devices are replacing standard lead-frame packages. Multiple stacked die packages such as package-in-package (PiP) and package-on-package (PoP) meet the demand for greater circuit density and improved electrical performance since they interface directly with solder bumps, solder land pads, or solder bumped pads.
However, to achieve these benefits, these packages contain multiple die stacked one on top of the other, with multi-level wire bonding or multi-level wafer bumping all within a single packaged device. Such increased level of complexity provides unique challenges for package inspection and quality control process qualification during device packaging and subsequent assembly. In particular, these more complicated packages now have the opportunity to exhibit defects both internal to the package as well as when assembled with the substrate or PCB. Such defects can include cracks, missing connections, interfacial voiding, wire bonding defects and/or die interface issues.
Computerized Tomography
In certain cases 2D X-ray inspection may be limited in what it can analytically provide when inspecting complex, multi-level 3D packages and is increasingly being complemented by computerized tomography (CT). CT is an imaging method where mathematical geometric processing is used to generate a 3D virtual model of a device by taking a large series of individual 2D X-ray images as the object is rotated about a single axis of rotation. Once the CT model has been produced, it allows ‘virtual micro-sectioning’ by investigating any two-dimensional plane within the entire model as well as real-time manipulation of the 3D model. This allows complete examination of features or defects within a device or package that would otherwise remain hidden by multi-level interconnections such as the cracked solder bumps within a multi-layered device (Figure 3).
Computerized tomography can also detect interfacial voiding within multi-layer devices since it is difficult to determine the exact location of voiding without using 3D CT imaging.
Complementary Techniques
Since flip chip solder bumps are small objects, they can be easily concealed by larger solder bumps or solder balls which makes the option of 3D imaging useful. Two-dimensional and 3D imaging work together as complementary inspection techniques within modern X-ray inspection systems where they can switch between 2D and 3D modes in a matter of minutes. This allows the benefits of both techniques — 2D being very fast and 3D helping to resolve obscured details and potential hidden defects. Both techniques have the added benefit of being non-destructive.2
Conclusion
Recent advancements in CT technology have made it an extremely useful tool in the analytical arsenal for the inspection of flip-chip devices and 3D packages. It enables complete viewing of interconnections with a package which otherwise may be obscured by other joints or objects when viewed only with 2D x-ray inspection. The combination of 2D x-ray and CT analysis offers powerful analytical capabilities need for the complete inspection of flip-chip devices and stacked packages.
References
1. Cole-Johnson, Sally, “Flip-Chip Changes on the Horizon,” Semiconductor International, July 2008
2.Bernard, David and Krastev, Evstatin, “Investigating Defects in 3D Packages Using 2D and 3D X-ray Inspection,” SMTA International, August 2008
EVSTATIN KRASTEV, Ph.D., applications manager for semiconductor packaging and PCB inspection, Dage Precision Industries, may be contacted at [email protected].
By Ritwik Chatterjee, Ph.D., and Rao R. Tummala, Ph.D, Packaging Research Center—Georgia Institute of Technology
There is a need for miniaturization at the IC, module (or sub-system), and system levels. At the IC level, scaling continues as it has over the last four decades according to Moore’s Law. In addition, 3D chip stacking technology with through silicon vias (TSVs) has garnered a lot of attention recently due to its potential in improving the performance, form factor, cost, and reliability at the sub-system or module level. There is still much research and development required to bring this hetero-integration technology to cost-effective implementation with the required reliability and performance needs. In addition to the module level, we must focus on performance, form factor, cost, and reliability of the entire system.
Although active and stacked ICs are a highly functional and important component of the overall system, it is only one set of components; many other components including other actives, passives, power systems, wiring, and connectors must be considered in a complete system. As a result, there is a need to think at module and system levels and this need is largely unmet by the current research in the areas of thru-Si vias (TSVs), 3D stacking, and wafer level packaging. This requires a multidisciplinary, collaborative, and global effort.
To develop 3D integration and system technologies beyond the present research activities, the Packaging Research Center (PRC) at Georgia Institute of Technology (Atlanta, GA) has teamed up with IZM Fraunhofer (Berlin, Germany) and the Korea Advanced Institute of Science and Technology (Deajeon, Republic or Korea) to develop technologies that address the present needs in TSV, 3D stacking, interposer technology, and system needs of miniaturization and monolithic integration of components. Although the initial research effort will focus on TSVs, 3D stacking and Si interposer with better electrical and thermal performance, greater system reliability, and reduced form factor and cost, it will go far beyond this to realize a truly seamless wafer system module (WSM). The WSM, as shown in Figure 1, will incorporate aspects of 3D stacking, as well as Si package with embedded passive components.
To achieve the system integration technologies proposed, we identified the technology needs in five basic areas:
In each of these areas, there is already ongoing activity by many researchers, but there are many issues that are unresolved.
Design and Test
There is a need for design tools, especially those that allow the simultaneous modeling of electrical and thermal effects from nanometer to millimeter scale. Signal switching noise in power delivery networks, hybrid equalization of signals, low cost parametric test methodologies, and novel design and structure of wiring and TSVs are other topics to be researched in this program.
Si Interposer Research
Si interposer research will focus on replacing the organic packaging by means of wafer level packaging (WLP) with TSV technologies with a Si core. We will use both typical semiconductor processing technologies (DRIE, CVD, PVD), as well as packaging technologies (dry film lamination, electroless plating, etc.) to achieve high-density wiring and I/O with better thermal and mechanical properties and reduced cost.
Low-cost TSV and Stack Bonding
There is currently a lot of research and development activity in the area of TSVs and stack bonding, however, issues of thermo-mechanical reliability and cost have not yet been resolved. Several fundamental projects are proposed within this program to improve the reliability and significantly reduce the cost of TSV technology. This includes the fabrication of novel TSV structures and geometries, novel process technologies that result in faster unit process steps or the elimination of process steps in the overall integration, and novel interconnection technologies that will result in increased reliability and reduced cost of stacking die.
Embedded Actives and Passives
Embedded active and passive technologies are a very important area of research in enabling system miniaturization. Research projects in embedded antennas, high-density and high-Q capacitors and inductors, embedded die-stack in Si cavities, and embedded actives in build0-up layers will be pursued.
System Interconnection
System interconnection research will primarily focus on second level (substrate to board) interconnections. As we move to Si packaging substrates, the thermo-mechanical reliability of first level (IC to package) interconnections is less of a concern than second level interconnections. In the 3D-ASSM program, novel structures and processes are proposed to address the thermo-mechanical reliability of substrate to board interconnections.
In addition to the twenty-four fundamental research projects proposed in the five technology areas described, technology demonstrator test vehicles will also be designed and fabricated. These test vehicles are for the purpose of incorporating and demonstrating the technologies developed in the various research projects. The test vehicles will include 3D stack bonding, Si interposer/package, and WSM.
As part of developing the 3D-ASSM program, workshops have been held in Atlanta, Berlin, Tokyo, and Seoul, with strong participation of over 250 scientist, engineers, and managers from over 80 semiconductor IC, packaging, system and supply chain companies. A final meeting to finalize the 3D-ASSM program prior to launch is planned for October 28 and 29 in Atlanta. To discuss the program in greater detail, please contact contact Ritwik Chatterjee
by James Montgomery, News Editor, Solid State Technology
Sept. 9, 2008 – Tom Mika, CEO of Tegal, gives SST some further insights into his company’s proposed acquisition of Alcatel Micro Machining Systems’ (AMMS) deep reactive ion etch (DRIE) and other technologies, part of a plan to tap into higher-growth markets in 3D IC packaging and MEMS devices — including how the company will leverage its existing presence in MEMS, and finding the balance between R&D and production-tool capabilities, and fighting much larger competitors.
– Filling in the etch portfolio. Tegal already has several MEMS customers for both critical and noncritical etch, plus “some IDMs who are getting more active in this arena,” Mika said. One benefit: Tegal can etch platinum and other noble metals, and platinum tends to be incorporated into MEMS devices, he noted.
– Production, not R&D. With ~1500 tools in the field, some still running in fabs for 20 years, and frequent listing on VLSI’s annual customer satisfaction report card, Tegal has a good handle on how to serve customers’ production requirements, and this is part of why it is making inroads into DRIE, Mika said. “When we do the noncritical etches, we do pretty much everything other than deep,” he said. “Over past 2-3 years, customers are ready to say that the tools that they’re buying from leading suppliers are fine for R&D, but when they’re going to production that’s a different story.” He mentioned DRIE market leader STS as an example, specifically started to do R&D tools, “but that’s not where we see the business, where we want to focus.”
This likely means trimming some of the R&D side of AMMS’ business. “We will serve R&D labs where there are strategic commitments that we think are reasonable to make,” Mika said, “but we’re really going to focus on the value of our providing production-worthy tools. Some of those sales, whatever they were, probably will not accrue to us.”
– Where the costs come out. Tegal also has eyes to where it can pare away some costs with this deal. The deal will be acretive in the next fiscal year (April 2009), Mika said, with gross margins exceeding incremental operating expenditures. But he also quickly said that there are “very significant opportunities to increase gross margins” without raising prices: bring AMMS’ manufacturing from France to the US (where Tegal has trimmed its own manufacturing overhead by 50% in the past couple of years), as well as procurement to source through existing suppliers. AMMS outsourced most of its manufacturing to local partners, and Mika said the combined Tegal/AMMS would continue to source some critical components from there, but “by and large the majority of OEM components we’ll procure here, and fab parts the same, and do it in-house.” He noted that having internal assembly and final test is a big advantage; “outsourcing only works when you’re the size of Lam or Applied.”
In another cost-streamlining move, the company also will re-engineer/redesign some AMMS system architecture (though they’ll still be available as-is). For example, the chuck is designed to be flexible for R&D usage, but can be reworked to be engineered on Tegal’s process module and tighter production specs. Also, AMMS’ cluster tool uses a Brooks platform, while Tegal has its own cluster module, Mika said.
– Only the small survive… Some might suggest that making a market move into a market seen as key to one’s future comes with a price — $5M in Tegal’s case, and only $1M of that in cash, and a scan of financial sites suggests some investors see that as a bargain. But the reality is, for semiconductor capital equipment firms, particularly microcaps like Tegal, “you have to preserve cash,” Mika pointed out. “The environent is not one that’s very friendly to raising capital.” He added that the stock-heavy deal also is hoped to spur both sides to future growth — “there’s nothing like ownership in stock to get both sides focused on the right objective: long-term creation of value.”
– …while swimming with the big fish. Mika acknowledged that while the DRIE segment has some small players (e.g. STS), it’s also caught the eye of larger etch firms like Lam and Applied Materials, who certainly target big business on production floors. So where does Tegal fit into this crowding market? “Tegal is well positioned to at least be an alternative supplier,” he said. “We really have to be in markets that are where Lam, Applied, etc. don’t really mind.” While those two will duke it out in 300mm production, “the business nwo is really 200mm, certainly in MEMS and also in integrated devices.” 3D TSVs are also in the 300mm arena, but “probably a couple of years away,” he said, “and that’s where we expect to see Lam as a formidable competitor.”
Mika also downplayed the increased interest in MEMS among pureplay foundries (e.g. TSMC and UMC), as something of a “marginal application — “in a downturn they get interested. Some customers are seduced by that…others are not.” Foundries tend to reuse existing toolsets for new work like this (as with nonvolatile memory), so this is one area where Tegal isn’t as strong, Mika noted. — J.M.
Sept. 7, 2008 – Tegal Corp.’s proposed acquisition of Alcatel Micro Machining Systems’ (AMMS) deep reactive ion etch (DRIE) and plasma-enhanced chemical vapor deposition (PECVD) products is “a critical part of our growth strategy” to extend into higher-growth markets in 3D IC packaging and MEMS devices, the company asserts.
Under terms of the deal, Tegal will buy Alcatel Micro Machining Systems’ (AMMS) and Alcatel-Lucent’s deep reactive ion etch (DRIE) and plasma-enhanced chemical vapor deposition (PECVD) products and related IP in a $5M in cash-and-stock transaction. Tegal will continue development of the AMMS DRIE product line, including integrating AMMS’ process modules on its recently-introduced Compact bridge platform, and the completion of a 300mm process chamber. AMMS will continue to support its existing installed base of DRIE tools in use by MEMS and IDMs, and Tegal will assume responsibility for AMMS’ joint development programs with key customers and research and academic institutions.
The deal is “an important strategic move for Tegal” to aggressively pursue the large high-growth markets in MEMS and semiconductor device manufacturing, said Thomas Mika, chairman/president/CEO of Tegal, in a statement. Gilbert Bellini, president of AMMS, who will be appointed to Tegal’s board of directors, added that Tegal will particularly target “the rapidly expanding markets for 3D wafer-level packaging applications.”
Deep reactive-ion etching (DRIE) is a highly anisotropic etch process used to create deep, steep-sided holes and trenches in wafers (>20:1 aspect ratios). Current end-markets include a variety of MEMS and power devices, memory stacking (flash and DRAM), logic, RF-SiP, and CMOS image sensors. But now attention is also turning to MEMS devices and through-silicon via (TSV) for advanced packaging applications.
In an online Q&A, Tegal explained that its MEMS customers already using its materials etch and PVD systems have been asking the toolmaker to get a foothold in DRIE for over two years. Moreover, the DRIE segment targeting these markets is largely packed with smaller companies — including AMMS, which according to Yole Développement was the #2 DRIE tool supplier in 2007 (see Fig. 1) — and is poised for significant growth through 2012 (~$148M to $434M, a 31% CAGR) (see Fig. 2). Most of the suppliers base their technology on the Bosch process; exceptions include Ulvac, Shinko Seiki, and Oxford Instruments.
About six people are expected to move over to Tegal from AMMS in Annecy, France, over a six-month transition period, with a total of 6-10 people in various positions added over several months. The addition of AMMS will not change Tegal’s manufacturing strategy, which is to outsource some critical components but bring as much assembly/final test into its Petaluma, CA facility.
by Fran
The second-generation SUSS MA300, from SUSS MicroTec is a highly automated mask aligner platform for 300-mm and 200-mm wafers. Specifically designed for 3D packaging, it features a dedicated alignment kit for creating 3D interconnects for applications like chip stacking and 3D image sensor packaging. It also targets wafer bumping and wafer level packaging (WLP) applications, but can be used for other technologies where geometries in the range of 5 and 100 µm must be exposed.
In addition to the standard topside alignment with accuracies down to 0.5 µm a 3D-alignment platform enables bottom side and infrared alignment for 300-mm based 3D packaging lithography applications such as etch masks for TSVs and dicing streets, backside redistribution layers (RDLs), or bumping applications. Bottom-side alignment enables processing of double-sided structured wafers, while infrared alignment option allows for handling of opaque, yet IR-transparent materials such as adhesives, particularly for thin wafer handling or encapsulation applications.
Unlike steppers proximity mask aligners are very efficient when exposing very thick layers. Mask aligners offer large process windows because they don’t have the depth of focus limitations known from projection systems. SUSS MicroTec Lithography GmbH, Munich, Germany. www.suss.com
(July 14, 2008) — IMEC and Qualcomm collaborate on 3D packaging technologies; IPC meets internationally to discuss urgent trends; iNEMI releases recommendations for lead-free alloy alternatives.
European independent nanoelectronics research institute IMEC partnered with Qualcomm Incorporated for the research group’s industrial affiliation program (IIAP) on 3D integration. Qualcomm and IMEC researchers in the program will collaborate to understand and develop solutions for the use of 3D technologies in future wireless products. Qualcomm represents fabless IC providers in the supply chain, completing the group of industry players for the 3D integration program, said Luc Van den hove, chief operation officer (COO) at IMEC. Strong industry collaboration among foundries, IDMs, packaging and assembly companies, and equipment suppliers at IMEC will push the development of innovative 3D products forward, added Van den hove. IMEC’s 3D integration program explores 3D technology and design for application in various domains, focusing on 3D wafer-level packaging (WLP) and 3D stacked ICs. The 3D system-on-chip (SoC) design research program provides insights to its benefits, costs, challenges, and solutions. The program will also include the development and demonstration of the IP and tools necessary for designing in three dimensions. Other partners in IMEC’s 3D integration program are Amkor, Infineon, Intel, Micron, NEC, NXP, Panasonic, Qimonda, Samsung, ST Microelectronics, Texas Instruments, and TSMC. For more information, visit www.imec.be.
IPC — Association Connecting Electronics Industries will host a two-day event in Berlin, Germany, to discuss trends driving the electronics industry. The IPC EMS Management Council Meeting and Executive Market & Technology Forum Conference, September 10–11, 2008, and feature content experts from around the world presenting on a number of strategic topics to help participants discern and prepare for future industry opportunities and shifts. On September 11, the Executive Market & Technology Forum Conference, hosted in partnership with the European Institute for Printed Circuits (EIPC), will start with Philipp Ehmer, an economist with Deutsche Bank AG, presenting an economic forecast and industry outlook. Delegates will also receive new data on demand trends for PCBs and assemblies, photovoltaics updates, and new opportunities in the industrial electronics market. Major OEMs’ technology roadmaps are driving environmental trends through the supply chain, a topic that will be examined alongside the results of an IPC-commissioned study on environmental megatrends. The European EMS Management Council Meeting on September 10 will focus on business strategy and management issues. Topics include the best practices of lead-free processes, the five most important elements in an EMS contract, and battling counterfeit components. IPC plans to address specific concerns of decision makers in the industry and offer answers on how to manage businesses more effectively. The IPC Government Relations Committee will hold a special open forum to discuss industry regulatory concerns, and IPC staff and members will discuss the outcome of IPC’s recent RoHS review process meeting in Brussels. For more information, see www.ipc.org/2008Berlin, www.ipc.org, and www.eipc.org.
IPC also released “Introduction to Box Build,” an instructional DVD, as part of its media training library. The DVD covers documentation, subassemblies and components, tools, handling, safety issues, and step-by-step process details for building a typical electronic product. It includes optional English subtitles for hearing-impaired and ESL students and comes with a Leader’s Guide, review questions, and IPC training certificates.
The International Electronics Manufacturing Initiative (iNEMI) consortium outlined a set of recommendations to help the electronics industry manage lead-free alloy alternatives. iNEMI’s recommendations support the guidelines developed by the EMS Forum to address these same issues. iNEMI notes that the most commonly used lead-free alloys, SAC 305/405, do not meet all of industry’s needs for all applications, and new alloy solutions continue to be introduced. iNEMI recommends a convergence of lead-free alloys; industry-standard assessment methodologies for solders; performance guidelines; updated standards; and knowledge of the differences between alloys. New solder formulations and fluxes on the market pose several challenges in the manufacturing process and industry needs some way to manage these challenges and limit their impact, iNEMI reports. Consortium members supporting these recommendations include Agilent Technologies, Celestica, Cisco, Delphi Electronics & Safety, Flextronics International, Hewlett-Packard (HP), Intel Corporation, Jabil Circuit, Motorola, Plexus Corp., Sanmina-SCI, Sun Microsystems, and Texas Instruments. For additional information, visit www.inemi.org.