Category Archives: 3D Integration

TowerJazz, the global specialty foundry leader, and Newsight Imaging, today announced production of Newsight’s advanced CMOS image sensor (CIS) chips and camera modules, customized for very high volume LiDAR and machine vision markets, combining sensors, digital algorithms and pixel array on the same chip. Newsight’s CIS chips are used in ADAS (advanced driver assistance systems) and autonomous vehicles as well as in drones and robotics.

LiDAR (Light Detection and Ranging), a detection system which works on the principle of radar, but uses light from a laser, is considered a must have for autonomous driving due to its high resolution at long distances, and market growth is expected to be exponential once L4/L5 autonomous vehicles become mainstream. IHS estimates the automotive LiDAR semiconductor market will reach $1.8 billion by 2026, with 37% CAGR (2018-2026). By utilizing TowerJazz’s advanced 180nm technology, featuring a wide range of customizable pixel architectures and technologies, Newsight is well-positioned to address the vast opportunities in the automotive market as well as in the security, defense, medical, industrial, and consumer markets.

Newsight’s innovative image sensor chips are ideal for high volume, competitive applications requiring cost effectiveness, low power consumption, high performance, and analog and digital integration. The NSI3000 sensor family, currently in mass production at TowerJazz’s Migdal Haemek, Israel facility, offers extremely high sensitivity pixels, enabling the replacement of expensive CCD (charge-coupled device) sensors in many applications and is designed for programmable high frame rate speeds, allowing better analysis and reaction to events.

In addition, Newsight’s innovative NSI5000, currently in development with TowerJazz at its fab in Israel, is an integrated LiDAR solution for long-range applications and includes a top DSP (digital signal processor) controller which enables complex calculations for depth and machine vision. NSI5000 is used in cutting-edge 3D pulsed based LiDARs for automotive applications and is based on Newsight’s eTOF (enhanced time-of-flight), which bridges the gap between short-distance iTOF (indirect time-of-flight) and the long distance automotive requirement, by extending the dynamic range while retaining high accuracy.

“We chose TowerJazz for its advanced pixel technology, specially customized for our CMOS image sensor chips addressing very high volume markets. Together with our technology, we were able to demonstrate a 4X better sensitivity to our customers. TowerJazz’s CIS offering is proven in the industry and we are pleased to manufacture locally in Israel with a leader in the global analog foundry space,” said Eli Assoolin, Chief Executive Officer, Newsight Imaging.

“With our high-end pixel offering, tailored to specific product and application needs, we are able to provide advanced technology used for high dynamic range CMOS sensors and solutions for the growing LiDAR and automotive markets. We are very happy to work closely with Newsight Imaging to provide market leading solutions and achieve quick time to market. They have shown to be an extremely fast-moving customer and we have a lot of confidence in their success,” said Dr. Avi Strum, TowerJazz Sr. Vice President and GM, CMOS Image Sensor Business Unit.

The spread of digital camera applications in vehicles, machine vision, human recognition and security systems, as well as for more powerful camera phones will drive CMOS image sensor sales to an eighth straight record-high level this year with worldwide revenues growing 10% to $13.7 billion, following a 19% surge in 2017, according to IC Insights’ 2018 O-S-D Report—A Market Analysis and Forecast for Optoelectronics, Sensors/Actuators, and Discretes. The new 375-page report shows nothing stopping CMOS image sensors from continuing to set record-high annual sales and unit shipments through 2022 (Figure 1).

Figure 1

Figure 1

CMOS image sensors continue to take marketshare from charge-coupled devices (CCDs) as embedded digital-imaging capabilities expand into a wider range of systems and new end-use applications, says the 2018 O-S-D Report.  With the smartphone market maturing, sales growth in CMOS image sensors slowed to 6% in 2016, but strong demand in other imaging applications played a major factor in boosting revenues by 19% to $12.5 billion last year.  Sales of CCD and other image sensor technologies fell 2% in 2017 to about $1.6 billion after rising 5% in 2016, according to the new IC Insights report.

Overall, CMOS image sensors grabbed 89% of total image sensor sales in 2017 compared to 74% in 2012 and 54% in 2007.  Unit shipments of CMOS imaging devices represented 81% of total image sensors sold in 2017 compared to 64% in 2012 and 63% in 2007.  New CMOS designs keep improving for a variety of light levels (including near darkness at night), high-speed imaging, and greater resolution as well as integrating more functions for specific applications, such as security video cameras, machine vision in robots and cars, human recognition, hand-gesture interfaces, virtual/augmented reality, and medical systems.

In new smartphones, CMOS image sensors are also seeing a new wave of growth with the increase of dual-lens camera systems (using two sensors) for enhanced photography.  Cellular camera phones accounted for 62% of CMOS image sensor sales in 2017, but that marketshare is forecast to slip to 45% in 2022. Automotive CMOS image sensors are projected to grow the fastest among major end-use applications through the five-year forecast shown in the new O-S-D Report, rising by a compound annual growth rate (CAGR) of 38.4% to about 15% of total CMOS image sensor sales in 2022 ($2.8 billion) while camera phone-generated revenues are expected to rise by a CAGR of just 2.2% to $8.6 billion that year.

Semtech Corporation (Nasdaq:SMTC), a supplier of high performance analog, mixed-signal semiconductors and advanced algorithms, today announced it has acquired substantially all the assets of IC Interconnect, Inc. (“ICI”), a privately-held, U.S.-based company that provides contract wafer bumping and related services to the electronics industry. The acquisition is expected to add 42 employees located in Colorado Springs, Colo.

Under the terms of the purchase agreement, Semtech acquired ICI assets for a cash purchase price of approximately $7 million and assumed certain obligations going forward. Semtech funded the purchase price using its current cash assets. The Company does not expect the deal to have any material impact to its earnings.

Next-generation Protection platforms require advanced technological capabilities to deliver the right combination of the highest performance and smallest footprint. Semtech and ICI have demonstrated their ability to produce market leading solutions such as the Semtech Z-Pak™ platform with more than 25 billion Z-Pak-based devices shipped into high-end consumer applications such as smartphones, wearables and tablets.

“The addition of ICI is aimed at further enhancing our U.S. R&D capabilities by developing and ramping our next-generation Z-Pak platform – the Z-UltraTM platform,” stated Mark Costello, Vice President and General Manager of Semtech’s Protection Products Group. “The “Z-Ultra” platform will significantly enhance Semtech’s ability to address new challenges created by further shrinking of silicon geometries and will drive quantum improvements in system-level performance over our current platform.”

“ICI has combined manufacturing process innovation and operational excellence to deliver cost-effective wafer level packages to Semtech since 2001 and we are now excited to become part of the Company,” stated Curt Erickson, President of ICI.

SEMI Industry Research and Statistics, and Jan Vardaman, TechSearch International

The global semiconductor packaging materials market reached $16.7 billion in 2017. While slower growth of smartphones and personal computers – the industry’s traditional drivers – is reducing material consumption, the slowdown was offset by strong unit growth in the cryptocurrency market in 2017 and early 2018. Flip chip package shipments into the cryptocurrency market, while providing a windfall to many suppliers, are not expected to remain at high levels, SEMI, the industry association representing the global electronics manufacturing supply chain, and TechSearch International reported in The Global Semiconductor Packaging Materials Outlook.

The outlook shows that, despite growth in automotive electronics and high-performance computing, continuing price pressure and declining material consumption will constrain future material revenue growth to steady single-digits, with the materials market forecast to reach $17.8 billion in 2021. IC leadframes, underfill, and copper wire are among the materials segments that will see single-digit unit volume growth through 2021.

Laminate substrate suppliers participating in the sale of flip chip substrates for cryptocurrency saw volume increases in 2017, but this segment continues to be battered by increased use of multi-die solutions and the shift to wafer level packages (WLPs), including fan-out WLP, slowing growth. Wafer-level packaging (WLP) dielectrics and plating chemistry suppliers will experience stronger revenue growth as the adoption of advanced packaging continues.

Over the next several years, advances in the semiconductor materials market will present a number of opportunities driven by trends including:

  • Continued adoption of FO-WLP including FO-on-substrate solutions with high density geometries down to 2µm lines and spaces
  • Liquid crystal polymer (LCP) under consideration as a possible material option because of its good electrical performance and low moisture absorption, especially for mmWave applications such as 5G
  • Adoption of low-cost package solutions such as MIS and other routable-QFN technologies
  • PPF QFN volumes are rising with automotive applications, driving a requirement for roughened plating to deliver needed reliability
  • Expansion of photoresist plating capability for selective plating of leadframes
  • Thermally enhanced and high-voltage mold compounds for power and automotive devices
  • Thermally conductive die attach materials other than solder die attach for power applications

Report highlights include:

  • Laminate substrates represent the largest revenue segment of the materials market with more than $6 billion in sales for 2017.
  • Overall leadframe shipments are forecast to grow at a 3.9 percent CAGR from 2017 through to 2021, with LFCSP (QFN type) experiencing the strongest unit growth, an 8 percent CAGR.
  • Following five years of decline, gold wire shipments increased in both 2016 and 2017 though represent just 37 percent of the total bonding wire shipments in 2017.
  • Liquid encapsulant revenues totaled $1.3 billion in 2017 with single-digit expected through 2021. LED packaging applications are driving the revenue growth over the forecast period though downward pricing pressures are a constant in the market.
  • Die attach material revenues reached $741 million in 2017 with single digit growth to 2021. DAF materials will experience higher unit growth, though downward pricing trends continue.
  • Solder ball revenues reached $231 million in 2017. The revenue outlook depends on fluctuations in metal pricing.
  • The wafer-level plating chemical market was put at $263 million in 2017 with strong growth through 2021. RDL and Cu pillar will be the key growth segments.

SEMI and TechSearch International, Inc. teamed up again to develop the 8th edition of the Global Semiconductor Packaging Materials Outlook, a comprehensive market research study on the semiconductor packaging materials market. Interviews were conducted with more than 130 semiconductor manufacturers, packaging subcontractors, fabless semiconductor companies, and packaging material suppliers to gather information for the report. The report covers the following semiconductor packaging materials segments: substrates, leadframes, bonding wire, mold compounds, underfill materials, liquid encapsulants, die attach materials, solder balls, wafer level package dielectrics, and wafer-level plating chemicals.

For more information and to purchase the report, click here.

To meet growing market demand for high-density 2.5D and 3D stacked semiconductor solutions, Silicon Valley-based ALLVIA, Inc. has expanded its in-house capabilities to include the formation of through-quartz vias (TQV) ranging from 15 microns in diameter and 100 microns deep to 50 microns in diameter and 250 microns deep. ALLVIA’s new TQV solution significantly improves the performance of 3D-ICs by creating IC interconnects with lower parasitic capacitance than can be achieved with the earlier generation of through-silicon via (TSV) technology.

he company had been outsourcing the production of via holes in the fused silica (quartz) that it uses, but its newly added capability brings all via-drilling operations in-house, expanding ALLVIA’s intellectual property and reducing the cost of production. The company will continue to apply its proprietary technology to fill the high-aspect-ratio via holes with copper plating to fabricate finished interposer products.

Sergey Savastiouk, CEO of ALLVIA, said, “Performing our own via drilling in fused silica allows us to improve turnaround times and production volumes for our customers while also delivering better quality using our state-of-the-art technology for copper plating, chemical mechanical polishing and deep via thin-film deposition.”

In addition to providing via foundry services, ALLVIA applies its technology in manufacturing and selling ultra-thin quartz interposers that form the electrical connections between a silicon chip and a printed circuit board.

TowerJazz today announced the release of its 300mm 65nm BCD (Bipolar-CMOS-DMOS) process, the most advanced power management platform for up to 16V operation and 24V maximum voltage.  This technology is manufactured in TowerJazz’s Uozu, Japan facility, with best-in-class quality and cycle time, and is based on the Company’s 300mm 65nm automotive qualified flows.

This platform provides significant material competitive advantages for any type of power management chip up to 16V regardless of application, including a wide variety of products such as: PMICs, load switches, DC-DC converters, LED drivers, motor drivers, battery management, analog and digital controllers, and more. IHS Markit Power IC Analyst, Kevin Anderson forecasts a $9.4 billion available market, which this technology addresses, in 2018 with continual growth.

TowerJazz’s 65nm BCD process is leading this low voltage market segment with the highest power efficiency, very small die size, best digital integration capability; and superior cost effectiveness through both the smallest aerial footprint and the lowest mask count.

The process includes four leading edge power LDMOS transistors: 5V, 7V, 12V and 16V operation, each with the best available Rdson and Qgd parameters. In addition to the new aforementioned cost and figure of merit benchmarks, multiple chips can be integrated to a single monolithic IC solution replacing a multiple chip module for an improved system cost structure and system performance.

TowerJazz’s power transistors are fully isolated to withstand high currents, all with an ultra-low Rdson, e.g. less than 1mΩ*mm² for the 5V LDMOS. For products which operate at the megahertz (MHz) switching frequencies, the 65nm BCD power transistors benefit from a very low Qgd down to 2.6mΩ*nC. In addition, very low metal resistance is achieved using a single or dual 3.3um top thick copper. The 65nm BCD also offers aggressive 113Kgate/mm² 5V digital density and an 800Kgate/mm² 1.2V digital library.

“This new 65nm BCD platform establishes TowerJazz as a technology leader in the related growing markets for up to 16V power applications,” said Shimon Greenberg, Vice President and General Manager of Power Management & Mixed-Signal/CMOS Business Unit, TowerJazz. “Best addressing the vast low voltage power management market segment, we are experiencing very high interest from early adopter customers and plan a mass production ramp by the fourth quarter of 2018.”

TowerJazz will be exhibiting at ISPSD, the 30th IEEE International Symposium on Power Semiconductor Devices and ICs on May 13-17, 2018 in Chicago, USA.

Mentor, a Siemens business, has announced that several tools in its Calibre® nmPlatform and Analog FastSPICE (AFS™) Platform have been certified by TSMC for the latest versions of TSMC’s 5nm FinFET and 7nm FinFET Plus processes. Mentor also announced it has updated its Calibre nmPlatform tools in support of TSMC’s Wafer-on-Wafer (WoW) stacking technology. These Mentor tools and TSMC’s new processes will enable mutual customers to more quickly deliver silicon innovations in high-growth markets.

“Mentor continues to increase its value to the TSMC ecosystem by offering more features and solutions in support of our most advanced processes,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “By continuing to innovate leading-edge electronic design automation (EDA) technologies for our new processes, Mentor is again proving its commitment to TSMC and our mutual customers.”

Mentor’s enhanced tools for TSMC 5nm FinFET and 7nm FinFET Plus processes

Mentor worked closely with TSMC to certify various tools in Mentor’s Calibre nmPlatform – including Calibre nmDRC™, Calibre nmLVS™, Calibre PERC™, Calibre YieldEnhancer, and Calibre xACT™ – for TSMC’s 5nm FinFET and 7nm FinFET Plus processes. These Calibre solutions now have new measurements and checks including, but not limited to, supporting extreme ultraviolet (EUV) lithography requirements jointly defined with TSMC. Mentor’s Calibre nmPlatform team is also working with TSMC to address physical verification runtime performance by enhancing scalability of multi-CPU runs to improve productivity. Mentor’s AFS platform, including the AFS Mega circuit simulator, is also now certified for TSMC’s 5nm FinFET and 7nm FinFET Plus processes.

Mentor’s enhanced tools for TSMC’s WoW stacking technology

Mentor made enhancements to its Calibre nmPlatform tools in support of the WoW packaging. Enhancements include DRC and LVS signoff for dice with backside through-silicon vias (BTSV), interface alignment and connectivity checks for die-to-die as well as die-to-package stacking. Further enhancements include parasitic extraction on backside routing layers, interposers with through-silicon vias (TSVs), and interface coupling.

Calibre Pattern Matching for TSMC’s 7nm SRAM Array Examination Utility

Mentor worked closely with TSMC to integrate Calibre Pattern Matching into TSMC’s 7nm SRAM Array Examination Utility. This flow helps customers to ensure their SRAM implementations are constructed to meet process requirements. This automation enables customers to tape out successfully. The SRAM Array Examination Utility is available to TSMC’s customers for 7nm production.

“TSMC continues to develop innovative silicon processes that enable our mutual customers to bring to market many of the world’s most advanced ICs,” said Joe Sawicki, vice president and general manager of the Design-to-Silicon Division at Mentor, a Siemens business. “We, at Mentor, are proud to not only lead the way in certifying our platforms for TSMC’s latest processes, we are also proud of our close partnership with TSMC in developing new technologies that help customers achieve production silicon faster.”

To learn more, visit Mentor at booth #408 at TSMC’s Technology Symposium on May 1, 2018 at the Santa Clara Convention Center in Santa Clara, California.

 

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced its continued collaboration with TSMC to further 5nm and 7nm+ FinFET design innovation for mobile and high-performance computing (HPC) platforms. The Cadence® digital, signoff and custom/analog tools have achieved the latest Design Rule Manual (DRM) and SPICE certification for the TSMC 5nm and 7nm+ processes. The corresponding process design kits (PDKs) are now available for download.

5nm and 7nm+ Digital and Signoff Tool Certification

Cadence provides a fully integrated digital flow from implementation to final signoff that has been certified by TSMC for the latest versions of the 5nm and 7nm+ processes. For the 7nm+ process, the Cadence full-flow includes the Innovus™ Implementation System, Quantus™ Extraction Solution, Tempus™ Timing Signoff Solution, Voltus™ IC Power Integrity Solution, Voltus-Fi Custom Power Integrity Solution, Physical Verification System (PVS) and Layout-Dependent Effect (LDE) Electrical Analyzer. For the 5nm process, the Cadence certified tools include the Innovus Implementation System, Quantus Extraction Solution, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution, Voltus-Fi Custom Power Integrity Solution, the layout vs. schematic (LVS) function in PVS and LDE Electrical Analyzer.

Cadence digital and signoff features available for the 7nm process are also available for the 5nm and 7nm+ process. Some of these features include cut-metal handling throughout the design flow, via-pillar support, clock mesh and bus-routing. These capabilities can enable customers to successfully design mobile and HPC systems with improved power, performance and area (PPA) while reducing iterations and achieving their cost and performance objectives.

In addition, Cadence has delivered new enhancements focused on EUV support at key layers and associated new design rules that specifically support the 5nm and 7nm+ processes. Some of the other newest enhancements for the 7nm+ process include cell pin support, Self-Heating Effect (SHE) and heatsink support.

Specifically for the 5nm process, Cadence digital and signoff tools offer high-resistance resistor support, router compliance for new rules and new extraction support including additional resistor layer modeling and other middle end-of-line (MEOL) features.

5nm and 7nm+ Custom/Analog Tool Certification

The certified custom/analog tools include the Spectre® Accelerated Parallel Simulator (APS), Spectre eXtensive Partitioning Simulator (XPS), Spectre RF, and Spectre Circuit Simulation, as well as the Virtuoso® product suite, which consists of the Virtuoso Schematic Editor, Virtuoso Layout Suite and Virtuoso Analog Design Environment.

By using the latest capabilities and design methodologies included with the Virtuoso Advanced-Node Platform, customers can achieve an improvement in custom physical design throughput versus traditional non-structured design methodologies, while maintaining a similar effort and cycle time via the advanced capabilities in the Virtuoso and Spectre tools.

Cadence delivered several custom/analog enhancements specifically to support the TSMC 5nm and 7nm+ process technologies. For example, Cadence introduced an accelerated custom placement and routing methodology, which enables customers to improve productivity and meet their power, multiple patterning, density and EM requirements. In addition, Cadence introduced universal poly grid snapping, asymmetric coloring support and voltage-dependent rule support for power/ground rails specifically for the 5nm process.

5nm and 7nm+ Library Characterization Tool Flow

The Virtuoso Liberate™ Characterization Solution and the Virtuoso Variety™ Statistical Characterization Solution have been validated to deliver Liberty libraries including advanced timing, noise and power models. The solutions utilized innovative methods to characterize Liberty Variation Format (LVF) models, enabling accurate process variation signoff for low-voltage applications and the ability to create EM models enabling signal EM optimizations and signoff.

“Using the latest design rules and PDKs, our customers have started designing complex SoCs on our most advanced process technologies,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “Through the continuation of our collaboration with Cadence, we’ve certified their tools and flows for 5nm and 7nm+ designs, which can enable our customers to achieve their design goals within a fast, predictable timeline.”

“Over the past few years, Cadence has taken on a broader role in facilitating advanced-node adoption due to the optimizations and performance improvements across our digital and signoff and custom/analog tool suites,” said Dr. Chin-Chi Teng, corporate vice president and general manager in the Digital & Signoff Group at Cadence. “We’ve expanded our collaboration with TSMC by developing tools and flows that support their 5nm and 7nm+ process technologies, and our latest TSMC certifications are enabling us to support customers using the most advanced process nodes.”

Synopsys, Inc. (Nasdaq: SNPS) today announced certification of the Synopsys Design Platform with TSMC’s latest Design Rule Manual (DRM) for advanced 7-nanometer (nm) FinFET Plus process technology. With several test chips taped out and production designs currently under development by multiple customers, this certification by TSMC enables a wide range of designs from high-performance computing and high-density to low-power mobile applications using the Synopsys Design Platform.

This certification is a milestone for TSMC’s extreme ultraviolet lithography (EUV) process that enables significant area savings while maintaining high performance when compared to non-EUV process nodes.

The Synopsys Design Platform, anchored by Design Compiler Graphical synthesis and IC Compiler™ II place-and-route tools, has been enhanced to take full advantage of TSMC’s 7-nm FinFET Plus for high-performance designs. Design Compiler Graphical is capable of automatically inserting via pillar structures to boost performance and prevent signal electromigration (EM) violations, and can pass the information to IC Compiler II for further optimization. It also automatically applies non-default rules (NDR) during synthesis and performs layer-aware optimization to improve design performance. These optimizations, including IC Compiler II bus routing, continue throughout the place-and-route flow to meet stringent delay-matching requirements of high-speed network.

PrimeTime® timing analysis advanced waveform propagation (AWP) and parametric on-chip variation (POCV) technologies have been optimized to address increased waveform distortion and non-Gaussian variation effects of higher performance and lower voltage operation. In addition, PrimeTime’s physically-aware signoff has been expanded to support via-pillars.

Synopsys has enhanced the Design Platform to perform physical implementation, parasitic extraction, physical verification, and timing analysis to support TSMC’s WoW technology. The physical implementation flow with IC Compiler II provides full support for wafer staking designs, from initial die floorplan preparation to placement and assignment of bumps to implementation of die routing. Verification is done by IC Validator for DRC/LVS checks, and Synopsys’ StarRC tool performs parasitic extraction.

“Ongoing collaboration with Synopsys and early customer engagements on TSMC’s 7-nanometer FinFET Plus process technology are delivering differentiated platform solutions that help our mutual customers bring innovative new products to market faster,” said Suk Lee, senior director of the Design Infrastructure Marketing Division at TSMC. “Certification of the Synopsys Design Platform enables our mutual customers’ designs in our first mass-production, EUV-enabled technology.”

“Our collaboration with TSMC on their mass-production 7-nanometer FinFET Plus process allows companies to confidently begin designing their increasingly large SoC and multi-die chips with the highly-differentiated Synopsys Design Platform,” said Michael Jackson, corporate vice president of marketing and business development for the Design Group at Synopsys. “Certification on TSMC’s 7-nanometer FinFET Plus process enables our customers to benefit from significant power, performance, and area improvements of an advanced EUV process, while accelerating time-to-market for their differentiated products.”

Samsung Electronics Co., Ltd. today announced that it has begun mass producing 10-nanometer (nm)-class* 16-gigabit (Gb) LPDDR4X DRAM for automobiles. The latest LPDDR4X features high performance and energy efficiency while significantly raising the thermal endurance level for automotive applications that often need to operate in extreme environments. The 10nm-class DRAM will also enable the industry’s fastest automotive DRAM-based LPDDR4X interface with the highest density.

“The 16Gb LPDDR4X DRAM is our most advanced automotive solution yet, offering global automakers outstanding reliability, endurance, speed, capacity and energy efficiency,” said Sewon Chun, senior vice president of memory marketing at Samsung Electronics. “Samsung will continue to closely collaborate with manufacturers developing diverse automotive systems, in delivering premium memory solutions anywhere.”

Moving a step beyond its 20nm-class ‘Automotive Grade 2’ DRAM, which can withstand temperatures from -40°C to 105°C, Samsung’s 16Gb LPDDR4X is Automotive Grade 1-compliant, raising the high-end threshold to 125°C. By more than satisfying the rigorous on-system thermal cycling tests of global auto manufacturers, the 16Gb LPDDR4X has enhanced its reliability for a wide variety of automotive applications in many of the world’s most challenging environments.

Adding to the degree of reliability under high temperatures, production at an advanced 10nm-class node is key to enabling the 16Gb LPDDR4X to deliver its leading-edge performance and power efficiency. Even in environments with extremely high temperatures of up to 125°C, its data processing speed comes in at 4,266 megabits per second (Mbps), a 14 percent increase from the 8Gb LPDDR4 DRAM that is based on 20nm process technology, and the new memory also registers a 30 percent increase in power efficiency.

Along with a 256 gigabyte (GB) embedded Universal Flash Storage (eUFS) drive announced in February, Samsung has expanded its advanced memory solution lineup for future automotive applications with the 10nm-class 16Gb LPDDR4X DRAM, commercially available in 12Gb, 16Gb, 24Gb and 32Gb capacities. While extending its 10nm-class DRAM offerings, the company also plans on bolstering technology partnerships for automotive solutions that include vision ADAS (Advanced Driver Assistance Systems), autonomous driving, infotainment systems and gateways.