Category Archives: 3D Integration

The semiconductor industry showed impressive figures in 2017: +21.6% YoY growth to reach about US$ 412 billion. Without any doubt, the industry is entering a new age, where innovation and disruption are the key words. In addition to mobile, Yole Développement (Yole) analysts identified emerging mega-drivers that are step by step changing our world. Big data, AI, 5G, HPC, IoT, smart automotive, industry 4.0, datacenters and more, all mega-trends becoming part of our day to day life, with a direct impact on the semiconductor industry and its supply chain. In its latest report, Status of the Advanced Packaging Industry, Yole predicts an impressive US$39 billion advanced packaging market in 2023 with 7% CAGR.

“The advanced packaging is also driven by the wind of changes, due to the impressive impact of the megatrends,” explained Emilie Jolivet, Division Director, Semiconductor & Software at Yole. “Yole and NCAP China have decided to combine their expertise this year again to propose the Advanced Packaging & System Integration Technology Symposium in Shanghai, prior NEPCON China. This Shanghai edition will be the place to be to understand the industry evolution and measure the impact of the megatrends”.

NCAP CHINA and Yole build an innovative program fully dedicated to the advanced packaging industry: the Advanced Packaging & System Integration Technology Symposium takes place in Shanghai, China, from April 22 to 23, 2019, prior to NEPCON China 2019. During 2 days, all packaging aspects, including Panel Level, Fan-Out, SiP , Advanced Substrates and 3D Technology, will be discussed. A focus on key applications such as AI, HPC, memory, transportation (48V, EV/HEV , embedded die packaging platform, PCB , advanced substrates), 5G and consumer (WLP and Fan-Out platforms) will be at the heart of the conference.

Both partners invite you to meet the leading executives and gain an in-depth understanding of the market evolution! More info.

Mega-trends create huge business opportunities amongst various advanced packaging platforms. Therefore, advanced packaging technologies are just ideal for fulfilling numerous performance and complex heterogeneous integration needs.

“Two advanced packaging roadmaps are foreseen: scaling and functional,” asserts Santosh Kumar, Principal Analyst & Director Packaging, Assembly & Substrates, Yole Korea. “And the semiconductor industry is developing products for both of them. Advanced packaging is seen as a way to increase the value of a semiconductor product, adding functionality, maintaining/increasing performance while lowering cost…”

Both roadmaps developed by the Semiconductor & Software team at Yole, hold more multi-die heterogeneous integration, called SiP, and higher levels of package customization in the future. A variety of SiP solutions is developing in both high and low end, for consumer, performance and specialized applications. Heterogeneous integration has clearly created opportunities for both the substrate and WLP based SiP.

More than that. The advanced packaging supply chain is also involved in this fantastic story. Leading companies, startups, R&D institutes, the worldwide advanced packaging industry is playing the game. In order to expand the business, explore new areas and prepare for future uncertainty, advanced packaging players are moving to different business models:

• Some IDMs such as Intel are entering the foundry business to leverage their front-end technology expertise and create additional revenue stream by utilizing their excess capacity. Samsung, SK Hynix are also part of the playground…
• OEMs , software and service companies are designing their own chips and controlling the supply chain of equipment & materials related to it. Betting on mega-trends such as AI, some OSATs are expanding into the fablite business model.
• Pure play foundries including TSMC, XMC, UMC and SMIC are entering the high-end packaging business to provide turnkey solution to their customers.
• OSATs, such as Amkor Technology, JCET/STATS ChipPAC, ASE, SPIL, Powertech Technology…, are directing considerable efforts in developing advanced wafer level and 3D IC packaging capability to support requirements for scaling & density. OSATs are expanding their testing expertise & traditional pure test players are investing in assembly and packaging capability.
• Substrate manufacturers are penetrating the advanced packaging area with panel-level fan-out packaging and embedded die in organic laminate.

It is a fact. Advanced packaging is at the heart of innovation. Mega-trend applications are bringing new challenges, and leading advanced packaging companies from all over the world will come to exchange ideas on their vision and future perspectives at the Advanced Packaging & System Integration Technology Symposium.

Dr. Cao LiQiang, NCAP’s CEO asserts: “Under the background of China 13th Five-Year Plan and Made in China 2025, local organizations, including NCAP, focus on the core technology development for semiconductor industry and make big progresses. Promoting international communication as well as global cooperation on advanced packaging is the goal shared by Yole and NCAP, and the reason why we insist to organize the activity and make it an annual big event. With good reputations, hot topics and insightful presentations, we firmly believe that 2019 symposium will be a success. Don’t miss the opportunity to learn technology trend and expand your business at China.”

Yole and NCAP have created an unprecedented program to understand the status of the advanced packaging industry and help the companies to be part of the ‘tomorrow’ industry. The Advanced Packaging & System Integration Technology Symposium is unique.

The RF GaN industry is showing an impressive growth with a 23% CAGR between 2017 and 2023, driven by telecom and defense applications. By the end of 2017, the total RF GaN market was close to US$380 million and 2023 should reach more than US$1.3 billion with an evolving industrial landscape (1). Telecom and defense are looking for innovative technologies and RF GaN-based devices are directly answering to the market demand.

Figure 1

Defense remains a major RF GaN market segment, as its specialized high-performance requirements and low price sensitivity offer many opportunities for GaN-based products. In 2017-2018, the defense sector accounts for more than 35% of the total GaN RF market, and the global defense market shows no signs of slowing down (1).

“We believe this important GaN market segment will continue growing along with GaN’s overall penetration rate,” asserts Hong Lin, PhD. Senior Technology & Market Analyst at Yole Développement (Yole), part of Yole Group of Companies.

Under this dynamic ecosystem, Yole’s partner, Knowmade, has deeply analyzed the RF GaN IP landscape and proposes today a dedicated report, RF GaN 2019 – patent landscape analysis. This report reveals the competitive landscape from a patent perspective. Key patent owners, IP & technology strategies, and future intents have been deeply analyzed by Knowmade’s analysts. This report details competitors’ strengths and weaknesses in terms of patents and technologies. It also proposes a comprehensive description of the technology trends and emerging technologies status.
GaN RF has been recognized by industrial companies and has clearly become mainstream. Leading players are increasing revenue very rapidly and this trend will remain for the next several years. From an IP perspective, American and Japanese players dominate the RF GaN IP ecosystem. So who are the leading RF GaN companies? What is the status of their patent portfolio? Do they have the right IP portfolios to face huge opportunities?…

Knowmade’s analysts invite you to discover the status of the RF GaN IP landscape.

“Cree (Wolfspeed) indisputably has the strongest IP position, especially for GaN HEMTs on SiC substrate,”comments Nicolas Baron, PhD., CEO and co-founder of Knowmade. “Sumitomo Electric, the market leader in RF GaN devices, is well positioned but far behind Cree.”

Furthermore, Sumitomo Electric has been slowing down its patenting activity while other Japanese companies like Fujitsu, Toshiba and Mitsubishi Electric are increasing their patent filings and thus today have strong patent portfolios as well.

Intel and MACOM are currently the most active patent applicants for RF GaN, both especially for GaN-on-Silicon technology, and are today the main IP challengers in the RF GaN patent landscape.
Other companies involved in RF GaN market, such as Qorvo, Raytheon, Northrop Grumman, NXP/Freescale, and Infineon, hold some key patents but do not necessarily have a strong IP position. CETC and Xidian University dominate the Chinese patent landscape with patents on GaN RF technologies targeting microwave and mm-wave applications. And the emerging foundry HiWafer, entered the IP landscape three years ago, is today the most serious Chinese IP challenger… American and Japanese companies are playing a key role on the RF GaN IP playground.

From a device perspective, Cree (Wolfspeed) has also taken the lead in the GaN HEMT IP race for RF applications… “The analysis of Cree’s RF GaN patent portfolio shows it can effectively limit patenting activity in the field and control the freedom-to-operate of other firms in most key countries,” explains Nicolas Baron from Knowmade.

Intel, which entered the GaN HEMT patent landscape later, is currently the most active patent applicant and it should strengthen its IP position in coming years, especially for GaN-on-Silicon technology. New entrants in the GaN RF HEMT related patent landscape are mainly Chinese players: HiWafer, Sanan IC and Beijing Huajin Chuangwei Electronics.
Other noticeable new entrants are Taiwan’s TSMC and Wavetek Microelectronics, Korea’s Wavice and Gigalane, Japan’s Advantest, and America’s MACOM and ON Semiconductor…

Under this new IP report, the technology intelligence and IP strategy consulting company, Knowmade, has selected and analyzed more than 3,750 patents published worldwide up to October 2018. These patents pertain to RF GaN epiwafers including GaN-on-SiC and GaN-on-Silicon, RF semiconductor devices, including HEMTs and HBTs , integrated circuits, including RFICs and MMICs , operating methods and packaging, for all functions, such as RF PAs , RF switches and RF filters and from radio frequencies <6GHz to microwaves >6GHz and mm-waves >20GHz. A detailed description of this IP report is available on Knowmade’s website.

KLA Corporation (NASDAQ: KLAC) today announced the appointment of Victor Peng to its board of directors.

Mr. Peng is president and chief executive officer of Xilinx, where he also serves as a member of the board of directors. Peng has over 30 years of experience leading technology transformation, defining and bringing to market FPGAs, SoCs, GPUs, high performance microprocessors and chip sets, and microprocessor IP products.

“We’re excited to have Victor Peng join the KLA board,” commented Edward W. (Ned) Barnholt, chairman of the board of KLA Corporation. “Victor is an accomplished semiconductor industry leader who brings significant business knowledge, technical expertise, and operational experience that will be invaluable to KLA as we execute our strategies for growth and market leadership.”

Peng joined Xilinx in 2008 and was named president and CEO of the company in January of 2018. Previously he was Xilinx’s chief operating officer, with responsibility for global sales, global operations and quality, product development, and product and vertical marketing. Prior to that, he served as the company’s executive vice president and general manager of Products, a position he held since July 2014. Mr. Peng previously held executive roles at AMD, ATI, and MIPS Technologies.

Peng serves on the board of the Semiconductor Industry Association. He earned a Bachelor of Science, Electrical Engineering from Rensselaer Polytechnic Institute and a Master of Engineering, Electrical Engineering from Cornell University. He holds four U.S. patents.

The semiconductor business is defined by rapid technological changes and the need to maintain high levels of investment in research and development for new materials, innovative manufacturing processes for increasingly complex chip designs, and advanced IC packaging technologies.

However, since the 1980s, the long-term trend has been toward a slowdown in the annual growth rate of research and development expenditures according to data presented in the new, 2019 edition of IC Insights’ McClean Report—A Complete Analysis and Forecast of the Integrated Circuit Industry (released in January 2019). Consolidation in the semiconductor industry has been a big factor contributing to lower growth rates for R&D expenditures so far this decade. In the most recent five-year span from 2013-2018, semiconductor R&D spending grew by CAGR of 3.6% per year, essentially unchanged from the 3.3% experienced from 2008-2013 (Figure 1).

Figure 1

IC Insights expects new challenges such as three-dimensional (3D) die-stacking technologies, growing complexities in end-use applications, and other significant manufacturing barriers to raise semiconductor R&D spending to a slightly higher growth rate of 5.5% per year in the 2018-2023 forecast period.

R&D spending trends discussed here cover expenditures by integrated device manufacturers (IDMs), fabless chip suppliers, and pure-play wafer foundries and do not include other companies and organizations involved in semiconductor-related technologies, such as production equipment and materials suppliers, packaging and test service providers, universities, government-funded labs, and industry cooperatives, such as IMEC in Belgium, the CAE-Leti Institute in France, the Industrial Technology Research Institute (ITRI) in Taiwan, and the U.S.-based Sematech consortium, which was merged into the State University of New York (SUNY) Polytechnic Institute in 2015.

With the value of more than 90 merger and acquisition agreements topping $250 billion since 2015, tremendous consolidation has been underway among semiconductor suppliers—many of them major IC companies—which have been cutting costs by hundreds of millions of dollars and leveraging “synergies,” meaning the elimination of overlapping expenditures (e.g., jobs, facilities, and R&D activities) in an attempt to achieve higher levels of productivity and greater profits. After rising just 1% in 2015 and 2016, total semiconductor R&D spending grew 6% in 2017 and increased 7% in 2018 to reach a new record- high level of $64.6 billion.

During the last 40 years (1978-2018), R&D expenditures have increased at a compound annual growth rate of 14.5%, slightly higher than the total semiconductor revenue CAGR of 12.0%. Since the year 2000, semiconductor R&D spending as a percent of worldwide sales has exceeded the 40-year historical average of 14.5% in all but four years (2000, 2010, 2017, and 2018). In these four years, lower R&D-to-sales ratios had more to do with the strength of revenue growth than weakness in research and development spending.

The inaugural SEMI 3D & Systems Summit opens today as the industry gathers for the latest insights and trends in 3D integration and systems for semiconductor manufacturing and applications. The 28-30 January summit in Dresden, Germany, highlights the future of intelligent systems powered by artificial intelligence (AI). To register, click here.

SEMI 3D & Systems Summit features a broad scope of topics aimed at driving business opportunities and innovation in areas including:

  • 3DIC Through-Silicon-Via (TSV) technology
  • 2.5D, 3D FO-WLP/e-WLB
  • Active and passive interposers
  • Stacked dies or stacked wafers
  • 3D alternative technologies
  • 5G Integration


Professor Hubert Lakner, director, Fraunhofer-Institute for Photonic Microsystems IPMS, will kick off the summit with his keynote Heterointegration – The Path to Future Complex Intelligent Systems. Lakner will explore connected intelligence opportunities arising from the transition to autonomous driving, the digitalization and electrification of cars, and the digitalization of industry and electrical power grids. These capabilities will be enabled by AI, improved cybersecurity, reinforced connectivity through 5G, edge computing, low-power components, sensors and power management.

Steffen Kroehnert, senior director, Technology Development, Amkor Technology Inc. will discuss advances in heterogeneous integration. The current wave of technology innovation in the semiconductor industry is largely driven by AI, deep learning, cloud computing and Internet of Things (IoT), with each of these leading-edge technologies sharing a common need: high-speed signaling with ultra-low latency/power and real time computational formulations. These capabilities require fully integrated functionality at the source, better known as the edge.

3D & System Summit Speakers

3D & Systems Summit speakers include experts from industry leaders such as Orbotech, GLOBALFOUNDRIES, Fraunhofer-Institute for Photonic Microsystems IPMS, EPIC – European Photonics Industry Consortium, McKinsey, System Plus Consulting, ASE Group, imec, DISCO HI-TEC EUROPE, STMicroelectronics, G-ray, Amkor, TU Dresden, Huawei, Fraunhofer IZM, AT&S AG, Deca Technologies and Miland.

Exhibitors Include Leaders in 3D Integration Microelectronics

The exhibition will showcase the most prominent names in 3D integration microelectronics manufacturing including ASE Group, Amkor Technology, Canon, Confovis, DISCO, FineTech, Fraunhofer IZM, FRT Metrology, Imec, LPKF, Optim Wafer Services, SPTS andXPERI. See the floorplan here.

3D & Systems Summit attendees are also invited to join the Symposium Panel Level Packaging 2019, organized by Fraunhofer IZM, 30 January, 14:00-18:00. Registration for the event is open. More details on the symposium are available here.

By Serena Brischetto

SEMI met with Martin Schrems, director of Strategy and Business Development at AT&S AG, to discuss Fan-Out technology trends ahead of SEMI 3D & Systems Summitin Dresden, Germany.

SEMI: What are the AT&S AG mission and vision and your role within the company?

Schrems: AT&S AG is evolving from a pure PCB manufacturer towards an interconnect solution provider. We can clearly see a continued trend towards miniaturization and modularization by (3D) integration of components such as integrated circuits and passives. Module sizes tend to increase by integrating more functions and system-level requirements. As a PCB maker, we have served such system-level requirements for a long time. Further integration offers opportunities to embed components in PCBs or substrates, offer layout and simulation services, as well as provide assembly and test services depending on specific customer requirements. As director of Strategy and Business Development, I work with my colleagues in AT&S, customers, and partners across the industry towards understanding and leveraging this major transformation in the electronics industry.

SEMI: What project are you currently working on that you think will make a difference in 2019?

Schrems: There are number of very exciting projects, many of them already involving AT&S contributions to module integration. Some of these projects involve key customers directly. We see exciting opportunities for integration of larger multi-function modules by combining PCB, substrate, and embedding core competences.

SEMI: The focus of your presentation at the 3D & Systems Summit will be on “Fan-Out System-in-Board technology enabling module and system-level integration.” What do you see as the key trend in this area?

Schrems: Fan-Out technologies are used to distribute I/O pad connections of nanoCMOS ICs over a larger area. This relaxes bump pitch and feature size requirements for subsequent system-level PCB interconnects. In some cases, Fan-Out layers already provide a substitute to currently used Flip-Chip substrates. Well-known examples are Fan-Out packages for application processors for smartphones. There is definitely a trend in the market towards Fan-Out for high-end processor applications. Advantages of such Fan-Out packages are shorter electrical connections and a reduced thickness.

However, one weakness of current Fan-Out packages is that only a limited number of components can be integrated due to mechanical stability challenges – a barrier to further component integration in larger modules. Currently, the only way to integrate more components is to use laminate-based PCBs and substrates with conventional Surface Mount Technology. Recent proposals like our “Fan-Out System-in-Board” (FO-SiBTM) technology are expected to provide an alternative Fan-Out packaging option at the board-level in the future.

SEMI: Please elaborate.

Schrems: Fan-Out capability and integration of more components – typically up to the 100 and more needed for electronics integration at system level – can be achieved simultaneously by combining technologies from the PCB and the packaging world. PCB laminates such as glass particles and organic materials provide mechanical stability for large boards. The recent introduction of substrate-like PCBs (mSAP) has already paved the way to cover applications that were reserved for substrates and classical packaging in the past.

With FO-SiBTM technology, we have taken it a step further and offer the option to integrate SAP substrate layers onto the PCB with lines/spaces below 10µm. FO-SiBTM makes it possible to directly contact nanoCMOS chips on PCBs without any intermediate substrates. Further adding Cu pillar technology at panel level will enable Fan-Out structures even for surface-mounted components, making recent R&D on panel-level Cu pillar technology very important. Through joint R&D, we can drive progress in the industry to further enable cost-effective heterogeneous 3D integration.

SEMI: What are your expectations for the 3D & Systems Summit in Dresden, and why do you recommend your members and other industry leaders to attend?

Schrems: The 3D summit is the high-level conference where key electronics industry players discuss major heterogeneous integration trends. Therefore, we very much appreciate the opportunities to exchange ideas across the supply chain including users, developers of integrated electronics hardware and tool manufacturers.

Serena Brischetto is a marketing and communications manager at SEMI Europe.

ZEISS today unveiled a new suite of high-resolution 3D X-ray imaging solutions for failure analysis (FA) of advanced semiconductor packages, including 2.5/3D and fan-out wafer-level packages. The new ZEISS systems include the Xradia 600-series Versa and Xradia 800 Ultra X-ray microscopes (XRM) for submicron and nanoscale package FA, respectively, as well as the new Xradia Context microCT. With the addition of these new systems to its existing family of products, ZEISS now provides the broadest portfolio of 3D X-ray imaging technologies serving the semiconductor industry.

“Throughout its 170-year history, ZEISS has pushed the frontiers of scientific research and advanced the start-of-the-art in imaging technologies to enable new industrial applications and technological innovations,” stated Dr. Raj Jammy, president, ZEISS Process Control Solutions (PCS) and Carl Zeiss SMT, Inc. “Now more than ever in the semiconductor industry, where package as well as device features are shrinking in all three dimensions, new imaging solutions are needed to quickly isolate failures in order to enable higher package yields. We are extremely pleased to announce this trio of new 3D X-ray imaging solutions for advanced semiconductor packaging, which provides our customers with a powerful high-resolution toolset to improve their failure analysis success rates.”

Advanced Packaging Requires New Defect Detection and Failure Analysis Methods
As the semiconductor industry approaches the limits of CMOS scaling, semiconductor packaging needs to help bridge the performance gap. To continue producing ever-smaller and faster devices with lower power requirements, the semiconductor industry is turning to package innovation through 3D stacking of chips and other novel packaging formats. This drives increasingly complex package architectures and new manufacturing challenges, along with increased risk of package failures. Furthermore, since the physical location of failures is often buried within these complex 3D structures, conventional methods for visualizing failure locations are becoming less effective. New techniques are required to efficiently isolate and determine the root cause of failures in these advanced packages.

To address these needs, ZEISS has developed a new suite of 3D X-ray imaging solutions that provides submicron and nanoscale 3D images of features and defects buried within intact structures in advanced package 3D architectures. This is enabled by rotating a sample and capturing a series of 2D X-ray images from different perspectives, followed by reconstruction of 3D volumes using sophisticated mathematical models and algorithms. An unlimited number of virtual cross-sections of the 3D volume may be viewed from any angle – providing valuable insight of failure locations prior to physical failure analysis (PFA). The combination of submicron and nanoscale XRM solutions from ZEISS provides a unique FA workflow that can significantly enhance FA success rates. ZEISS’s new Xradia Context microCT offers high contrast and resolution in a large field of view, using projection-based geometric magnification, and is fully upgradable to Xradia Versa.

New Imaging Solutions in Detail
Xradia 600-series Versa is the next generation of 3D XRM for non-destructive imaging of localized defects within intact advanced semiconductor packages. It excels in structural and FA applications for process development, yield improvement and construction analysis. Based on the award-winning Versa platform with Resolution at a Distance (RaaD) capability, Xradia 600-series Versa offers unsurpassed performance for high-resolution imaging of larger samples at long working distances to determine root causes of defects and failures in packages, circuit boards and 300 mm wafers. It can easily visualize defects associated with package-level failures, such as cracks in bumps or microbumps, solder wetting problems or through silicon via (TSV) voids. The 3D visualization of defects prior to PFA reduces artifacts and guides cross-section orientations, leading to improved FA success rates. Features include:

  • 0.5 micron spatial resolution, 40 nm min voxel size
  • Up to 2x higher throughput than Xradia 500-series Versa, achieved while maintaining high resolution with excellent source spot-size stability and thermal management control across the full kV and power range
  • Improved ease of use, including fast-activation source control
  • Ability to observe submicron structural changes within a package successively imaged at multiple reliability test read points

Xradia 800 Ultra brings 3D XRM to the nanoscale realm, producing images of buried features with nanoscale spatial resolution while preserving the volume integrity of the region of interest. Applications include process analysis, construction analysis and defect analysis of ultra-fine-pitch flip chip and bump connections – enabling process improvement for ultra-fine-pitch package and back-end-of-line (BEOL) interconnects. Xradia 800 Ultra enables visualization of the texture and volume of solder consumed by intermetallic compounds in fine-pitch copper pillar microbumps. Defect sites are preserved during imaging, enabling targeted follow-up analysis by a variety of techniques. The construction quality of blind assemblies, such as wafer-to-wafer bonded interconnect and direct hybrid bonding, can be characterized in 3D. Features include:

  • 150 nm and 50 nm spatial resolution (sample preparation is required)
  • Optional pico-second laser sample prep tool, enabling extraction of an intact volume sample (typically 100 microns in diameter) in under one hour
  • Compatibility with a wide range of options for follow-on analysis, including transmission electronic microscopy (TEM), energy dispersive X-ray spectroscopy (EDS), atomic force microscopy (AFM), secondary ion mass spectroscopy (SIMS) and nanoprobing

IC Insights is in the process of completing its forecast and analysis of the IC industry and will present its new findings in The McClean Report 2019, which will be published later this month.  Among the semiconductor industry data included in the new 400+ page report is an analysis of semiconductor merger and acquisition agreements.

The historic flood of merger and acquisition agreements that swept through the semiconductor industry in 2015 and 2016 slowed significantly in 2017 and then eased back further in 2018, but the total value of M&A deals reached in the last year was still nearly more than twice the annual average during the first half of this decade.  Acquisition agreements reached in 2018 for semiconductor companies, business units, product lines, and related assets had a combined value of $23.2 billion compared to $28.1 billion in 2017, based on data compiled by IC Insights.  The values of M&A deals struck in these years were significantly less than the record-high $107.3 billion set in 2015 (Figure 1).

Figure 1

The original 2016 M&A total of $100.4 billion was lowered by $41.1 billion to $59.3 billion because several major acquisition agreements were not completed, including the largest proposed deal ever in semiconductor history—Qualcomm’s planned purchase of NXP Semiconductor for $39 billion, which was raised to $44 billion before being canceled in July 2018.  Prior to the explosion of semiconductor acquisitions that erupted four years ago, M&A agreements in the chip industry had a total annual average value of $12.6 billion in the 2010-2014 timeperiod.

The two largest acquisition agreements in 2018 accounted for about 65% of the M&A total in the year.  In March 2018, fabless mixed-signal IC and power discrete semiconductor supplier Microsemi agreed to be acquired by Microchip Technology for $8.35 billion in cash.  Microchip said the purchase of Microsemi would boost its position in computing, communications, and wireless systems applications.  The transaction was completed in May 2018.  Fabless mixed-signal IC supplier Integrated Device Technology (IDT) agreed in September 2018 to be purchased by Renesas Electronics for $6.7 billion in cash.  Renesas believes the IDT acquisition will strengthen its position in automotive ICs for advanced driver-assistance systems and autonomous vehicles.  The IDT purchase is expected to be completed by June 2019.

Just two other semiconductor acquisition announcements in 2018 had values of more than $1 billion.  In October 2018, memory maker Micron Technology said it would exercise an option to acquire full ownership of its IM Flash Technology joint venture from Intel for about $1.5 billion in cash. Micron has started the process of buying Intel’s non-controlling interest in the non-volatile memory manufacturing and development joint venture, located in Lehi, Utah.  The transaction is expected to be completed in 2H19.  In September 2018, China’s largest contract manufacturer of smartphones, Wingtech Technology, began acquiring shares of Nexperia, a Dutch-based supplier of standard logic and discrete semiconductors that was spun out of NXP in 2017 with the financial backing of Chinese investors.   Wingtech launched two rounds of share purchases from the Chinese owners of Nexperia with a combined value of nearly $3.8 billion.  The company hopes to take majority ownership of Nexperia (about 76% of the shares) in 2019.

Rambus Inc. today announced it has acquired the assets of Diablo Technologies to broaden its portfolio in the hybrid DRAM and Flash memory markets. These patented innovations augment the existing Rambus NVDIMM portfolio and complement its high-bandwidth, low-power memory technologies. Specific terms of the deal are not disclosed.

For over ten years, Diablo Technologies was a pioneer in the development of NVDIMM technologies for high-speed, low-power, and low-latency bridging and switching products targeted at the server and storage markets. Having developed memory buffer and software solutions leveraging an all-Flash memory sub-system, Diablo Technologies enabled an architecture to rewrite the rules of data center performance and economics. Rambus’ investment in these technology areas provide a foundation for integrating existing DRAM and Flash along with emerging memories into advanced hybrid memory systems in the future.

Expanding emerging memory technology for high memory bandwidth interfaces is key to Rambus’ strategic core business. The company has also been collaborating with IBM to research hybrid memory systems, as announced previously.

“Adding these breakthrough innovations from Diablo Technologies will continue to grow Rambus’ leadership in non-volatile and hybrid DRAM and Flash memory technologies with foundational patents,” said Kit Rodgers, SVP of Technology Partnerships and Corporate Development, Rambus. “Diablo Technology’s patented innovations were ahead of their time and nicely complement our offerings for existing and new customers.”

By Emmy Yi

SEMI Taiwan Testing Committee founded to strengthen the last line of defense to ensure the reliability of advanced semiconductor applications.

Mobile, high-performance computing (HPC), automotive, and IoT – the four future growth drivers of semiconductor industry, plus the additional boost from artificial intelligence (AI) and 5G – will spur exponential demand for multi-function and high-performance chips. Today, a 3D IC semiconductor structure is beginning to integrate multiple chips to extend functionality and performance, making heterogeneous integration an irreversible trend.

As the number of chips integrated in a single package increases, the structural complexity also rises. Not only will this make identifying chip defects harder, but the compatibility and interconnection between components will also introduce uncertainties that can undermine the reliability of the final ICs. Add to these challenges the need for tight cost control and a faster time to market, and it’s clear that semiconductor testing requires disruptive, innovative change. Traditional final-product testing focusing on finished components is now giving way to wafer- and system-level testing.

In addition, the traditional notion of design for testing, an approach that enhances testing controllability and observability, is now coupled with the imperative to test for design, which emphasizes drawing analytics insights from collected test data to help reduce design errors and shorten development cycles. Going forward, the relationship among design, manufacturing, packaging, and testing will no longer be un-directional. Instead, it will be a cycle of continuous improvement.

This paradigm shift in semiconductor testing, however, will also create a need for new industry standards and regulations, elevate visibility and security levels for shared data, require the optimization of testing time and costs, and lead to a shortage of testing professionals. Solving all these issues will require a joint effort by the industry and academia.

“With leading technologies and $4.7 billion in market value, Taiwan still holds the top spot in global semiconductor testing market,” said Terry Tsao, President of SEMI Taiwan. “When testing extends beyond the manufacturing process, it can play a critical role in ensuring quality throughout the entire life cycle from design and manufacturing to system integration while maintaining effective controls on development costs and schedules. Taiwan’s semiconductor industry is in dire need of a common testing platform to enable the cross-disciplinary collaboration necessary for technical breakthroughs.”

The new SEMI Taiwan Testing Committee was formed to meet that need, gathering testing experts and academics from MediaTek, Intel, NXP Semiconductors, TSMC, UMC, ASE Technology, SPIL, KYEC, Teradyne, Advantest, FormFactor, MJC, Synopsys, Cadence, Mentor, and National Tsing Hua University to collaborate in building a complete testing ecosystem. The committee addresses common technical challenges faced by the industry and cultivates next-generation testing professionals to enable Taiwan to maintain its global leadership in semiconductor testing.

The SEMI Taiwan Testing Platform spans communities, expositions, programs, events, networking, business matching, advocacy, and market and technology insights. For more information about the SEMI Taiwan Testing platform, please contact Elaine Lee ([email protected]) or Ana Li ([email protected]).

Emmy Yi is a marketing specialist at SEMI Taiwan.  

This story originally appeared on the SEMI blog.