Category Archives: 3D Integration

A research collaboration between Osaka University and the Nara Institute of Science and Technology for the first time used scanning tunneling microscopy (STM) to create images of atomically flat side-surfaces of 3D silicon crystals. This work helps semiconductor manufacturers continue to innovate while producing smaller, faster, and more energy-efficient computer chips for computers and smartphones.

Spatial-derivative STM images with 200x200 nm^2 at Vs = +1.5 V. Flat terraces become brighter and edges darker. The downstairs direction runs from left ((110) top-surface) to right ((-1-10) back-surface). Credit: Osaka University

Spatial-derivative STM images with 200×200 nm^2 at Vs = +1.5 V. Flat terraces become brighter and edges darker. The downstairs direction runs from left ((110) top-surface) to right ((-1-10) back-surface). Credit: Osaka University

Our computers and smartphones each are loaded with millions of tiny transistors. The processing speed of these devices has increased dramatically over time as the number of transistors that can fit on a single computer chip continues to increase. Based on Moore’s Law, the number of transistors per chip will double about every 2 years, and in this area it seems to be holding up. To keep up this pace of rapid innovation, computer manufacturers are continually on the lookout for new methods to make each transistor ever smaller.

Current microprocessors are made by adding patterns of circuits to flat silicon wafers. A novel way to cram more transistors in the same space is to fabricate 3D-structures. Fin-type field effect transistors (FETs) are named as such because they have fin-like silicon structures that extend into the air, off the surface of the chip. However, this new method requires a silicon crystal with a perfectly flat top and side-surfaces, instead of just the top surface, as with current devices. Designing the next generation of chips will require new knowledge of the atomic structures of the side-surfaces.

Now, researchers at Osaka University and the Nara Institute of Science and Technology report that they have used STM to image the side-surface of a silicon crystal for the first time. STM is a powerful technique that allows the locations of the individual silicon atoms to be seen. By passing a sharp tip very close to the sample, electrons can jump across the gap and create an electrical current. The microscope monitored this current, and determined the location of the atoms in the sample.

“Our study is a big first step toward the atomically resolved evaluation of transistors designed to have 3D-shapes,” study coauthor Azusa Hattori says.

To make the side-surfaces as smooth as possible, the researchers first treated the crystals with a process called reactive ion etching. Coauthor Hidekazu Tanaka says, “Our ability to directly look at the side-surfaces using STM proves that we can make artificial 3D structures with near-perfect atomic surface ordering.”

The global CMOS image sensor market is expected to grow at a CAGR of more than 12% during the forecast period, according to Technavio’s latest market research.

In this market research report, Technavio covers the market outlook and growth prospects of the global CMOS image sensor market for 2017-2021. The market is further categorized into four application segments, including consumer devices, automotive, security, and industrial. The consumer devices segment accounted for close to 83% of the market share in 2016.

“The market is characterized by a technological shift from charged CCD sensors to CMOS because of the simple manufacturing process and low costs. Though CCD sensors offer better features, such as great light sensitivity and quality, their adoption is low because of their complicated design and high-power consumption. The consumer device segment will remain the key market driver during the forecast period owing to the increase in the demand for mobile-related applications,” says Chetan Mohan, a lead sensors research expert from Technavio.

CMOS image sensor market in Americas

The CMOS image sensor market in the Americas is expected to maintain its steady growth trajectory in the coming years. The early adoption of new technologies and gadgets drives the market growth. In addition, the region has a large consumer base for consumer electronics, such as tablets and smartphones.

The high rate of industrial automation in the US drives the demand for CMOS image sensors as they are widely used in automated manufacturing and process machinery. The US and Canada boast of a strong healthcare sector which will lead to demand for a large number of medical devices that are integrated with CMOS image sensors.

“The growing demand for camera-enabled phones in South America will drive the market in the region. The government in South America is also focusing on urbanization and improving healthcare sectors. The increasing use of these sensors in automobiles and medical equipment is expected to have a positive impact on the market in the region,” says Chetan.

CMOS image sensor market in APAC

The region is expected to grow at the highest CAGR, owing to the presence of many manufacturing units for consumer electronic devices. In addition, APAC has the largest customer base for consumer devices. Rising disposable incomes have led to increased consumer spending capacity, which has further fueled the demand for latest gadgets. China, Japan, Taiwan, South Korea, and India are the key revenue contributors to the market in the region. These countries have numerous consumer electronics manufacturing units.

The presence of numerous semiconductor manufacturers in Japan, Taiwan, Korea, and China, will fuel market growth. In addition, the availability of low-cost labor and setting up of production facilities by global vendors are factors that will have a positive impact on the market in the region.

CMOS image sensor market in EMEA

EMEA will exhibit the lowest growth compared with other regions because of the low concentration of image sensor manufacturers and small consumer base. Germany is among the leading nations in the region. The country has numerous leading car manufacturers that offer CMOS sensing technology in their vehicles. The technology ensures passenger safety and promotes the development of intelligent vehicle systems. The country plans to automate a majority of the industrial process by the end of the forecast period. Advanced R&D in the medical field will also drive the demand for image sensing technology. South Africa is expected to account for the highest contribution to the market share in this region.

The top vendors in the global CMOS image sensor market as highlighted in this market research analysis are:

  • Sony
  • Samsung
  • OmniVision Technologies
  • ON Semiconductor

The Semiconductor Industry Association (SIA) today announced worldwide sales of semiconductors reached $35.0 billion for the month of August 2017, an increase of 23.9 percent compared to the August 2016 total of $28.2 billion and 4.0 percent more than the July 2017 total of $33.6 billion. All major regional markets posted both year-to-year and month-to-month increases in August, and the Americas market led the way with growth of 39.0 percent year-to-year and 8.8 percent month-to-month. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“Global semiconductor sales were up significantly in August, increasing year-to-year for the thirteenth consecutive month and reaching $35 billion for the first time,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Sales in August increased across the board, with every major regional market and semiconductor product category posting gains on a month-to-month and year-to-year basis. Memory products continue be a major driver of overall market growth, but sales were up even without memory in August.”

Year-to-year sales increased in the Americas (39.0 percent), China (23.3 percent), Asia Pacific/All Other (19.5 percent), Europe (18.8 percent), and Japan (14.3 percent). Month-to-month sales increased in the Americas (8.8 percent), China (3.7 percent), Japan (2.8 percent), Asia Pacific/All Other (2.2 percent), and Europe (0.6 percent).

“With about half of global market share, the U.S. semiconductor industry is the worldwide leader, but U.S. companies face intense global competition,” said Neuffer. “To allow our industry to continue to grow and innovate here at home, policymakers in Washington should enact corporate tax reform that makes the U.S. tax system more competitive with other countries. The corporate tax reform framework released last week by leaders in Congress and the Trump Administration is an important step forward. We look forward to working with policymakers to enact corporate tax reform that strengthens our industry and the U.S. economy.”

Aug 2017

Billions

Month-to-Month Sales                              

Market

Last Month

Current Month

% Change

Americas

6.94

7.55

8.8%

Europe

3.20

3.22

0.6%

Japan

3.04

3.13

2.8%

China

10.68

11.08

3.7%

Asia Pacific/All Other

9.77

9.98

2.2%

Total

33.63

34.96

4.0%

Year-to-Year Sales                         

Market

Last Year

Current Month

% Change

Americas

5.43

7.55

39.0%

Europe

2.71

3.22

18.8%

Japan

2.73

3.13

14.3%

China

8.99

11.08

23.3%

Asia Pacific/All Other

8.35

9.98

19.5%

Total

28.22

34.96

23.9%

Three-Month-Moving Average Sales

Market

Mar/Apr/May

Jun/Jul/Aug

% Change

Americas

6.27

7.55

20.5%

Europe

3.11

3.22

3.8%

Japan

2.95

3.13

6.0%

China

10.25

11.08

8.1%

Asia Pacific/All Other

9.43

9.98

5.9%

Total

31.99

34.96

9.3%

Providing deep insights and perspectives on the challenges and opportunities in automotive electronics, the second edition of “FUTURECAR: New Era of Automotive Electronics Workshop” will be held November 8-10 at Georgia Tech in Atlanta, Georgia. SEMI (http://www.semi.org) and Georgia Tech, collaborators for the event, see unprecedented technical challenges and opportunities in electrical, mechanical and thermal designs, and new digital, RF, radar, LiDAR, camera, millimeter wave, high-power and high-temp technologies. The workshop will highlight rapid advancements in automotive electronics technologies and applications, and explore technical and business barriers and opportunities that are best addressed collectively across the supply chain.

The focus of the 2017 FUTURECAR workshop is on electronics in the car of the future. Autonomous driving, in-car smartphone-like infotainment, privacy and security, and all-electric cars will be among the topics presented, with particular emphasis on how these advancements impact devices and packaging with respect to materials, tools, processes, substrates, packages, components and integrated functions in R&D and in manufacturing. This event provides a unique opportunity for the semiconductor manufacturing and automotive supply chains to connect, collaborate and identify areas for new solutions.

The plenary session on November 8 will feature presentations from leading experts from Mercedes Benz, Porsche, Bosch, Qualcomm, SAE International and Yole Développement. The workshop sessions on November 9-10 include:

  • Power devices and packaging
  • High-temperature materials and reliability
  • Sensing electronics
  • Computing and communications
  • Student posters

FUTURECAR draws on the synergy between Georgia Tech in R&D and its industrial partners, as well as SEMI in global electronics manufacturing stewardship across the supply chain. Key to the depth of the workshop is support and expertise from the technical co-sponsors International Electronics Manufacturing Initiative (iNEMI), IEEE Electronics Packaging Society (IEEE EPS) and International Microelectronics Assembly and Packaging (IMAPS), as well as SAE International, the global association representing engineers and experts in the aerospace, automotive and commercial vehicle industries.

Workshop co-chairs are Prof. Rao Tummala, Georgia Tech; Bettina Weiss, SEMI; Grace O’Malley, iNEMI; Christian Hoffman (Qualcomm), IMAPS; and Patrick McCluskey, IEEE.

For more information on FUTURECAR 2017 and to register, please visit http://www.prc.gatech.edu/FUTURECAR

 

By Dr. Jeongdong Choe, Senior Technical Fellow, TechInsights

There has been a great deal of speculation around the composition of Intel’s Optane™ XPoint memory technology: PCM or ReRAM, selector, layouts, patterning technology, technology node, multi-stacked cell structure, die floor plan, interconnection to each electrode (wordlines and bitlines), functional blocks, scalability and process integration.

TechInsights set about to find answers. We have analyzed Optane’s memory cell structure, materials, cell array and memory peripheral array design, layouts, process flow and circuitry. Our Advanced CMOS Essential (ACE) analyses on Intel’s XPoint memory presents our complete findings and market trend predictions. The following paragraphs present some of the highlights.

Intel XPoint memory is based on PCM and selector memory (storage) cell elements. GST-based PCM, Ge-Se-As-Si based Ovonic Threshold Switch (OTS) and two memory cell stacked array architecture are common across Intel’s and Micron’s XPoint technologies.

We examined effective memory cell area efficiency vs. memory array efficiency, and compared it to current DRAM and NAND products. In our previous analysis on XPoint memory die, we found that memory density per die is 0.62 Gb/mm2 and memory efficiency is over 91%. The memory array efficiency, however, may not represent the reality because the memory peripheral and CMOS circuitry cover most of the die area.

We can define the effective cell area efficiency as a ratio of the real area of the cell memory elements (storage) to the total die area. For example, the effective memory cell area efficiency on Toshiba 15 nm 2D planar NAND is 43.9% due to excluding BC, CSL, SSL, GSL dummy wordlines and peripheral area on a die, while memory array efficiency is 72%. Figure 1 shows comparison of the effective memory cell area efficiency for 2D/3D NAND products from Toshiba/SanDisk (Western Digital), Micron/Intel, SK Hynix and Samsung, and 3D XPoint (OptaneTM from Intel).

Figure 1. A comparison of effective memory cell area efficiency on 2D/3D NAND and XPoint memory

Figure 1. A comparison of effective memory cell area efficiency on 2D/3D NAND and XPoint memory

When it comes to the effective unit cell size per 1 bit, NAND flash devices have been scaled down from 2D NAND (320 nm2) to 48L 3D NAND (145.8 nm2) or even to 64L 3D NAND (88.5 nm2) for Toshiba NAND products, while Intel OptaneTM two cell stacked XPoint memory has 800 nm2 (effectively 2F2) (Figure 2).

Figure 2. A comparison of effective unit cell area per bit on 2D/3D NAND and XPoint memory

Figure 2. A comparison of effective unit cell area per bit on 2D/3D NAND and XPoint memory

A comparison of memory density with DRAM products shown in Figure 3 illustrates that XPoint has higher memory density (0.62 Gb/mm2) than Samsung 1x nm (0.19 Gb/mm2), SK Hynix 2y nm (0.15 Gb/mm2) and Micron 20 nm (0.094 Gb/mm2) DRAM dice. Micron announced that the memory density of XPoint would be ten times higher than commercial DRAM products. This is true if we compare it with 30 nm class DRAM products, because most of the 30 nm class DRAM products from major DRAM manufacturers have 0.06 Gb/mm2 memory density. The first commercial XPoint memory die has three times (vs. Samsung 1x DRAM) or six times (vs. Micron 20 nm DRAM) higher memory density than those of current DRAM products.

Figure 3. A comparison of die size and memory density on DRAM (25nm/20nm/18nm) and XPoint memory

Figure 3. A comparison of die size and memory density on DRAM (25nm/20nm/18nm) and XPoint memory

We found that Intel introduced some innovative and compelling technologies on their first XPoint products such as PCM/OTS stack used for memory elements, GST based PCM, Ge-Se-As-Si based OTS and carbon based conductor and 2-bit cell stacked memory array with three electrodes. Intel successfully used a 20nm SADP double patterning technology to build a very uniform GST-based PCM/OTS memory square/island. Complete details on the of TechInsights’ XPoint memory analysis can be found here.

Click here to hear more from Dr. Choe and his TechInsights colleagues on 3D NAND.

By James Amano, International Standards, SEMI

The SEMI International Standards Committee, at their SEMICON West 2017 meeting, approved the transformation of the existing 3D Stacked IC Committee and Assembly & Packaging Committee into a single, unified 3D Packaging and Integration Committee. Emerging technologies will be accommodated into the scope of the new committee, as North American TC Chapter Co-Chair Sesh Ramaswami (Applied Materials) explains: “Multi-die integration, horizontally and vertically, leveraging substrate, fan-out, interposer and TSV technology is our future. Hence, the new charter and scope will enable the committee to be of more value to the industry.”

Charter:

To explore, evaluate, discuss, and create consensus-based specifications, guidelines, test methods, and practices that, through voluntary compliance, will:

  • include the materials, piece parts, and interconnection schemes, and unique packaging assemblies that provide for the communication link between the semiconductor chip and the next level of integration, either single- or multi-chip configurations. It relates to the technologies for heterogeneous and other multi-chip packaging such as Fan-out/Fan-in Wafer Level Packaging, Panel Level Packaging, Three-Dimensional Stacking IC, device embedded packaging, flexible electronics technology
  • promote mutual understanding and improved communication between users and suppliers, equipment, automation systems, devices, and services
  • enhance the manufacturing efficiency, capability and shorten time-to-market and reduce manufacturing cost

Scope:

To develop standards for semiconductor devices, including processed wafers, chips, or multi-chip configurations to the next level of integration, either in single- or multi-chip configurations.

  • materials needed for 3D applications, including prime silicon and glass wafers, temporary and permanent bonding material, specifications needed for processed wafers and/or chips to enter an integration step, etc.
  • the materials related to the elements of, interconnection schemes, and unique packaging assemblies that provide for the communication link between device and packaging.
  • the technologies for heterogeneous and other multi-chip packaging such as Fan-out/Fan-in Wafer Level Packaging, Panel Level Packaging, Three-Dimensional Stacking IC, device embedded packaging, and flexible electronics technology
  • metrologies to support these 3D integration and packaging technologies

Masahiro Tsuriya (iNEMI), Japan Co-Chair, further emphasizes “The new 3D Packaging & Integration Committee will be able to contribute to the advance of new, innovative semiconductor packaging technologies.”

The global committee currently has chapters active in Japan, North America, and Taiwan, which all meet throughout the year. To get involved, please join the SEMI International Standards Program at: www.semi.org/standardsmembership.

GLOBALFOUNDRIES is now delivering in volume its 14nm High Performance (HP) technology that will enable IBM’s next-generation of processors for server systems. The jointly developed 14HP process is specifically designed to deliver the ultra-high performance and data-processing capacity IBM needs to support its cloud, commerce, and enterprise solutions in the era of big data and cognitive computing. IBM announced general availability of the IBM Z on September 13.

14HP is the industry’s only technology to integrate a three-dimensional FinFET transistor architecture on a silicon-on-insulator (SOI) substrate. Featuring a 17-layer metal stack and more than eight billion transistors per chip, the technology leverages embedded DRAM and other innovative features to deliver higher performance, reduced energy, and better area scaling over previous generations to address a wide range of deep computing workloads.

The 14HP technology powers the processors that run IBM’s latest z14 mainframes. The underlying semiconductor process allows IBM customers to enable massive transaction scale of high-volume workloads, apply machine learning to their most valuable data, and rapidly derive actionable insights to enable intelligent decisions—all while delivering pervasive encryption that provides the ultimate in data protection.

“GlobalFoundries has been a strategic partner in the development of a custom semiconductor technology to enable the aggressive requirements of the processors for our newest server systems,” said Ross Mauril, general manager, IBM Z. “We are excited to bring this 14HP technology to our IBM Z product line.”

“GF and IBM together have an unmatched heritage of developing and manufacturing ultra-high performance SOI chips,” said Mike Cadigan, senior vice president of global sales and business development at GF. “This new generation of 14HP processors is another example of the close collaboration between our engineering teams to meet the demands of a new generation of server systems.”

“The 14HP technology leverages the proven 14nm FinFET high-volume experience of our Fab 8 facility in Saratoga County, N.Y.,” said Tom Caulfield, senior vice president and general manager of GF’s Fab 8. “We are in high volume production with a broad set of customer designs across a range of applications. Our mature and diverse manufacturing capability will enable IBM to bring its latest processor designs to market to service their broad customer base.”

Since the 2009 semiconductor downturn and strong 2010 recovery year, power transistor sales have been rocked by market volatility, falling in three of the last five years because of inventory corrections and drawdowns by systems makers worried about ongoing economic weakness and price erosion in some product categories. After recovering from a 7% drop in 2015, power transistor sales grew 5% in 2016 to $12.9 billion and are forecast to set a new record high this year with worldwide revenues rising 6% to $13.6 billion, according to IC Insights’ 2017 O-S-D Report—A Market Analysis and Forecast for Optoelectronics, Sensors/Actuators, and Discrete Semiconductors.

The expected 2017 growth in power transistor sales will be the first back-to-back annual increase in this semiconductor market segment in six years, and that will push dollar volumes past the current record high of $13.5 billion set in 2011. In 2012 and 2013, power transistors suffered their first back-to-back annual sales decline in more than three decades—dropping 8% and 6%, respectively—after rising 12% in 2011 and surging 44% in the 2010 recovery from the 2009 downturn year. The power transistor market then rebounded in 2014 with a strong 14% increase, only to drop 7% in 2015. In 2016, this semiconductor discretes market category began to stabilize and is expected to continue expanding at a modest rate in the next several years, based on IC Insights’ O-S-D Report forecast (Figure 1).

Power transistors are the primary growth engine in the $23 billion discrete semiconductor market because they play a vital role in controlling and conditioning electricity for all types of electronics—including a growing number of battery-operated systems. Worldwide efforts to reduce the waste of power in electric utility grids have significantly increased the importance of power transistors in consumer, commercial, and industrial systems. Renewable-energy applications (e.g., wind and solar systems) as well as electric and hybrid vehicles have also become important applications for power transistors in the last 15 years.

Figure 1

Figure 1

However, volatility in the first half of this decade resulted in an uncharacteristic drop in market size for power transistors during the last five years.  Between 2011 and 2016, power transistor sales fell by a compound annual growth rate of -0.9% compared to a 25-year historical annual average increase of 6.4% (between 1991 and 2016).  The 2017 O-S-D Report is projecting that worldwide power transistor sales will grow by a CAGR of 4.2% between 2016 and 2021, reaching $15.8 billion in the final year of the forecast.

All power transistor technology categories are expected to register sales growth in 2017 with MOS field effect transistor (FET) products increasing 6% to nearly $7.7 billion, insulated-gate bipolar transistor (IGBT) products also rising 6% to $4.1 billion, and bipolar junction transistor products growing 4% to about $875 million.  RF/microwave power transistors and module sales are forecast to rise 3% in 2017 to $960 million, according to the O-S-D Report.

Synopsys, Inc. (NASDAQ: SNPS) today announced that the Synopsys Design Platform has been fully certified for use on Samsung Foundry’s 28FDS (FD-SOI) process technology. A Process Design Kit (PDK) and a comprehensive reference flow, compatible with Synopsys’ Lynx Design System, containing scripts, design methodologies and best practices is now available. For Samsung Foundry’s latest differentiated process offering, support for bias throughout the Design Platform flow has been thoroughly verified and certified to achieve optimal power and performance tradeoffs.

“FD-SOI technology offers one of the best power, performance, and cost tradeoffs,” said Jaehong Park, senior vice president of the Foundry Solutions Team at Samsung Electronics. “Samsung Foundry’s 28FD-SOI technology allows designs to operate both at high and low voltage making it ideal for IoT and mobile applications. Moreover, the FD-SOI technology exhibits the best soft error immunity, and, therefore, is well suited for applications that require high reliability such as automotive. Availability of certified Synopsys Design Platform, PDK and reference flow will allow our mutual customers to accelerate adoption of our 28FDS technology.”

“Our long standing, close collaboration with Samsung Foundry starts very early, allowing Synopsys to refine tools and flows enabling customers to achieve desired performance and power targets,” said Michael Jackson, corporate vice president of marketing and business development for the Design Group at Synopsys. “Certification of the Synopsys Design Platform, complete with PDK and reference flow helps our mutual customers to rapidly design with confidence for Samsung Foundry’s 28-nm FD-SOI process.”

SEMICON Europa 2017 will take place in Munich for the first time, co-located with productronica (14-17 November in Munich, Germany). SEMICON Europa will showcase the critical issues shaping the entire electronics manufacturing supply chain. Fourexecutive keynotes will share their thought leadership on current opportunities for Europe: Maria Marced, president, TSMC Europe; Stefan Finkbeiner, CEO, Bosch Sensortec; and Frank M. Rinderknecht, founder and CEO of Rinspeed Inc.

“Innovations in semiconductor manufacturing are at the heart of the value chain driving innovations enabling key future growth drivers in Mobile, Automotive, Medical, passive and intelligent computing as well as AR and VR,” stated Laith Altimime, president, SEMI Europe. SEMICON Europa programs, sessions, and speakers will illuminate this year’s theme “Empowering Innovation and Shaping the Value Chain.”  Highlights of SEMICON Europa include:

  • Fab Management Forum: Quality Challenges – Solutions for Tomorrow ─ Topics include:Future of digital vehicles and requirements for quality and availability of semiconductors with Daimler AG, an analysis of Human failure and mindset change by European School of Management and Technology (ESMT) Berlin, and how innovative sensor and analytics solutions enable new applications in the fab of tomorrow by KINEXON GmbH.
  • Advanced Packaging Conference: Electronics Packaging and Test for Future Mobility ─With Yole Développement on the dynamics of the advanced packaging ecosystem, Robert Bosch GmbH on automotive, Infineon Technologies on packaging for automotive ─ challenges and solutions, RoodMicrotec GmbH on wafer and final test in the new era of electronics, and STMicroelectronics on packaging challenges for robust miniaturization.
  •  Power Electronics Conference: From Materials to Systems,The Latest Innovations ─Covering power electronics applications for Automotive by Fraunhofer Institute for Integrated Systems and Device Technology IISB, a forecast of the next five years to reveal how technology development will shape the power electronics market by Yole Développement, and  Cambridge University on Silicon and Wide bandgap devices in power electronics.
  • New! Materials Conference: Connected World ─ New Material Challenges and Solutions ─Includes a keynote by Christophe Maleville, SOITEC, on how to better optimize performance, power budget and cost to meet applications requirements; plus presentations from Volkswagen AG on the need for new industry alliances in automotive, FUJIFILM on maximum utilization of chemically amplified resist, and Dow Chemical on the information age and connectivity enabled by advanced electronic materials. The free Webinar “Connected World: New Material Challenges and Solutions – Market Update and Outlook“ is planned on 27 September.
  • New! European Connect2Car Forum ─ A new Forum in collaboration with SAE International. Insights for automotive OEM and supplier executives, consumer electronics leaders, mobile application developers, and aftermarket entrepreneurs focusing on enhancing the driver experience and accelerating the deployment of connected and autonomous vehicle technologies.
  • New! 2017FLEX Europe “Be Flexible” ─ New collaboration between FLEX and Fraunhofer EMFT. Insights on innovative solutions for flexible and stretchable systems by Würth Elektronik GmbH,  technology and applications of chip-film patch for hybrid systems in foil by IMS CHIPS, new capabilities and applications of flexible components by E Ink Corporation, and insight on how potentials of System-in-Package technologies will affect the future by Bosch.

SEMI and Messe München Joint Press Conference will take place on 14 November at 11:00-12:00, at Messe München Press Conference Center.