Category Archives: 3D Integration

IC Insights has just released its September Update to The McClean Report.  This 32-page Update includes a detailed look at the pure-play foundry market and an analysis of the historical DRAM price-per-bit trends.  Shown below is an excerpt from the Update that examines the IC technology trends in the pure-play foundry market.

In 2017, the 7% increase in the total pure-play foundry market is forecast to be almost entirely due to an 18% jump in <40nm feature size device sales (Figure 1).

Figure 1

Figure 1

Although expected to represent 60% of total pure-play foundry sales in 2017, the ≥40nm pure-play IC foundry market is forecast to be up only $0.2 billion this year.  In contrast, the 2017 leading-edge <40nm pure-play foundry market is expected to surge by a hefty $3.3 billion.  Moreover, not only is almost all of the pure-play foundry growth forecast to come from leading-edge production in 2017, most of the profits that are expected to be realized in the foundry market also forecast to come from the finer feature sizes as well.

TSMC is by far the technology leader among the major pure-play foundries.  In 2017, 58% of TSMC’s revenue is expected to come from <40nm processing, more than double percentage at GlobalFoundries and more than triple the share at UMC.  In total, TSMC is forecast to hold an 86% share of the total <40nm pure-play foundry market this year.

Illustrating how dominant TSMC is in the leading-edge pure-play foundry market, the company is expected to have almost 7x the dollar volume sales at <40nm as compared to GlobalFoundries, UMC, and SMIC combined this year ($18.5 billion for TSMC and $2.7 billion for combined total of GlobalFoundries, UMC, and SMIC).  In fact, 10% of TSMC’s total sales this year are forecast to be for its 10nm process technology.

In contrast to TSMC, SMIC only entered initial production of its 28nm technology in 4Q15, more than three years after TSMC first put its 28nm process into production.  In fact, only 7% of SMIC’s 2017 sales are expected to be from devices having 28nm feature sizes (the company does not offer a finer feature size at this time), which is the primary reason its revenue per wafer is so much less compared to TSMC.

By Zvi Or-Bach, President and CEO of MonolithIC 3D Inc.

On Sept 13, DARPA come out with Electronic Resurgence Initiative (ERI) programs. Quoting: “with an eye toward the times we now live in, [Gordon Moore] laid out the technical directions to explore when the conditions under which scaling will be the primary means for advancement are no longer met. A trio of simultaneously-released ERI BAAs—this one among them—parallel the research areas detailed on page three of Moore’s paper: materials and integration, architecture, and design. These new page-three-inspired investments, along with a series of related investments from the past year, comprise the overall Electronics Resurgence Initiative.”

Among these programs is the “Three Dimensional Monolithic System-on-a-Chip (3DSoC): Develop 3D monolithic technology that will enable > 50X improvement in SoC digital performance at power.”

In perfect timing, this year’s IEEE S3S 2017 at the Hyatt Regency at the San Francisco Airport will feature a comprehensive show case for monolithic 3D IC technologies.

At the start Al Fazio, Intel Senior Fellow, will give a plenary talk on how 3D NAND and 3D XPoint™ happened to be the trailblazing monolithic 3D IC technologies that have matured to volume production, taking over the fast growing memory market. The first day will end with two 3D IC focus sessions comprised of a mix of invited and submitted papers covering exotic technologies and the use of the emerging nano-wire transistor for 3D scaling.

The first half of the second day includes a collaborative event organized by Qualcomm and CEA Leti – the COOLCUBE/3DVLSI Open Workshop. The second half will include an open 3D tutorial providing full coverage of the various 3D integration technologies from TSV to Sequential Integrations.

The third day of the conference will include a full day with four sessions of invited and submitted talks on monolithic and other forms of 3D integration. These sessions will include a talk by us, MonolithIC 3D Inc., in which we will present a monolithic 3D technology that is ready to be rapidly deployed using the current transistor process. In that talk we will also describe how such an integration technology could be used to improve performance, reduce power and cost of most computer systems, suggestive of a 1,000x total system benefit.

In addition, the IEEE S3S conference will have full coverage of SOI and low power technologies, making it the place to be and to learn about alternative technologies to dimensional scaling. I am looking forward to seeing you at the S3S from October 16th thru 19th, 2017.

Flex Logix Technologies, Inc., a supplier of embedded FPGA IP and software, today announced it has won the TSMC Open Innovation Platform’s Partner of the Year Award 2017 in the category of New IP for its EFLX embedded FPGA IP product.

“We are honored to win this prestigious award as it highlights the close alignment with TSMC that Flex Logix has achieved with its EFLX platform: EFLX embedded FPGA is available for TSMC 40nm, 28nm and 16nm process nodes with array sizes from 100 to >100K LUTs with options for DSP and any size/type of embedded RAM,” said Geoff Tate, CEO and co-founder of Flex Logix. “Flex Logix has worked closely with TSMC since the company was founded in 2014 and is proud to meet TSMC’s rigorous standards as an IP Alliance Member.”

Embedded FPGA is a new type of semiconductor IP enabling high-volume chip designers to incorporate reconfigurable logic to allow chips to be updated even in-system to adapt to new standards, new protocols, new algorithms and to customize chips for customers faster and more cost effectively than mask changes.

The award was presented during a ceremony at this year’s TSMC Open Innovation Platform Ecosystem Forum on September 13, 2017 in Santa Clara. Tate and Senior Vice President of Engineering Cheng Wang accepted the award on behalf of Flex Logix.

Soitec, a designer and manufacturer of semiconductor materials for the electronics industry, is launching a pilot line to produce fully depleted silicon-on-insulator (FD-SOI) wafers in its Singapore wafer fab. This is the first stage in beginning FD-SOI production in Singapore and providing multi-site FD-SOI substrate sourcing to the global semiconductor market.

“Our decision to launch this FD-SOI line in Singapore as well as the decision we already made to ramp up our FD-SOI production in France are based on direct customer demand,” said Paul Boudre, CEO of Soitec. “These are very important milestones for Soitec and the expanding FD-SOI ecosystem. In Singapore, we plan to get full qualification at the customer level in the first half of 2019 and then increase capacity in line with market commitment.”

The FD-SOI ecosystem continues to strengthen and the use of FD-SOI technology is progressing. Multiple foundries, IDMs and fabless customers are engaged with a growing number of FD-SOI tape-outs and wafer starts. FD-SOI offers a unique value proposition for low-power applications, which makes it well suited for rapidly growing electronic market segments such as mobile processing, IoT, automotive and industrial.

Soitec reports that its investment in Singapore to launch its FD-SOI pilot line is approximately US$40 million, to be spent over a 24-month period.

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced new capabilities that complete its holistic, integrated design flow for TSMC’s advanced wafer-level Integrated Fan-Out (InFO) packaging technology. Additionally, Cadence has unveiled enhancements for TSMC’s chip-on-wafer-on-substrate (CoWoS) advanced packaging technology. The complete InFO flow and enhanced CoWoS design methodologies enable design teams to efficiently complete the development process, from planning to analysis across multiple dies.

Completed InFO Design Flow

The Cadence® tools that have been enhanced to complete the TSMC InFO flow include the Quantus™ QRC Extraction Solution, Physical Verification System (PVS), and the Voltus™ Sigrity™ Package Analysis solution. Additional tools in the flow include OrbitIO™ Interconnect Designer, System-in-Package (SiP) Layout, Sigrity XtractIM™ technology, Tempus™Timing Signoff Solution, Sigrity PowerDC™ technology and Sigrity PowerSI® 3D-EM Extraction Option. With the completion of the flow, system-on-chip (SoC) designers can now:

  • Create virtual interface blocks and automate parasitic extraction, enabling package-level cross-die timing analysis: Cadence provides the first available platform that offers cross-die coupling extraction via the Quantus QRC Extraction Solution and PVS, enabling InFO designers to efficiently complete timing analysis with the Tempus Timing Signoff Solution at the package level.
  • Perform power DC and root mean square (RMS) electromigration (EM) and signal EM analysis: The Voltus Sigrity Package Analysis solution provides an integrated platform for power analysis across multiple dies and InFO designs.

CoWoS Reference Flow Enhancements

Cadence has also developed enhancements to the TSMC CoWoS reference flow. The new capabilities within the CoWoS refence flow enable designers to perform:

  • Integrated electromagnetic interference (EMI) analysis that enables analysis of the CoWoS system: Cadence is now offering an updated Sigrity EMI flow with automatic design merging, enabling integrated EMI analysis, as well as broadband-frequency-dependent S-parameter simulation, allowing for E/H-field analysis of the CoWoS system.
  • Static/dynamic IR analysis from a single environment: Voltus IC Power Integrity Solution now allows designers to do static/dynamic IR analysis across die and silicon interposers concurrently, while also analyzing power EM (dynamic/static) and signal EM (peak/RMS/average) for both dies and interposers within a single tool environment.
  • Correct cross-die interface alignment among dies and interposers: The PVS design rule checking (DRC) and layout versus schematic (LVS) capabilities provide cross-die DRC and power/signal connectivity checks, ensuring the cross-die interface has the correct alignment among the dies and interposers.
  • Thermal analysis across the CoWoS package, allowing accurate thermal runway predictions and reduced EM pessimism: The Voltus IC Power Integrity Solution and Sigrity PowerDC technology enable designers to do layer-based thermal analysis across the CoWoS package, which includes automated power map generation for all die within the solution and layer-based temperature map generation.
  • Parasitic extraction for silicon interposers, enabling timing and electrical analysis: The Quantus QRC Extraction Solution offers performance RC extraction, generating Standard Parasitic Exchange Format (SPEF) data for cross-die timing analysis. Additionally, Cadence Sigrity XcitePI™ technology provides RCLK extraction for frequency domain, signal integrity and power integrity simulation.

“We see a strong demand from both mobile and high-performance computing customers wanting to quickly deploy systems based on TSMC’s advanced packaging technologies,” said Tom Beckley, senior vice president and general manager of the Custom IC & PCB Group at Cadence. “Through our close working relationship with TSMC, we have completed TSMC InFO design flow and enhanced TSMC CoWoS reference flow, enabling our mutual customers to further shorten design and verification cycle times so they can get to market faster.”

“The Cadence solution for InFO technology enables our customers to deliver designs with increased bandwidth within small form factors,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “With these enhancements, the integrated full-flow addresses the market need for faster design and verification cycles. Additionally, the new capabilities added to the Cadence solution for CoWoS supports our customers who want to utilize this holistic reference flow for advanced packaging projects.”

Flex Logix Technologies, Inc., the supplier of embedded FPGA IP and software, today announced that it has joined the TSMC IP Alliance Program included in TSMC’s Open Innovation Platform.

Flex Logix has worked closely with TSMC since Flex Logix was founded in 2014 and now has its EFLX Embedded FPGA IP and software tools available for TSMC 16FFC/FF+, TSMC 28HPM/HPC and TSMC 40ULP/LP. For each EFLX IP core in each process, Flex Logix has designed, fabricated and validated a validation chip to demonstrate full-speed, high utilization performance and power specs over the full temperature and voltage operating ranges. Flex Logix has worked with TSMC to ensure its documentation, design methodology, validation chip architecture and testing all meet TSMC’s rigorous standards to become an IP Alliance Member.

EFLX embedded FPGA arrays are available on these TSMC processes in a wide range of sizes from 100 LUTs to >100,000 LUTs with options for DSP/MAC and any type/size RAM. Flex Logix will implement EFLX embedded FPGA on any additional TSMC process node as TSMC customers request. Over time, Flex Logix expects EFLX to be available on every node from 180nm to 7nm.

“Flex Logix offers high density, high performance, scalable embedded FPGA,” said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division. “We see good customer activity and interest in this emerging Semiconductor IP category and are pleased to have Flex Logix as an IP Alliance Member.”

Embedded FPGA is a new type of semiconductor IP enabling high-volume chip designers to incorporate reconfigurable logic to allow chips to be updated even in-system to adapt to new standards, new protocols, new algorithms and to customize chips for customers faster and more cost effectively than mask changes. Applications for embedded FPGA exist for networking, wireless base station, data center, deep learning, microcontroller, IoT, aerospace/defense and a range of other markets.

“We are proud to be joining the TSMC IP Alliance and appreciate TSMC’s support in helping us achieve membership,” said Geoff Tate, CEO of Flex Logix. “Our customers are in fab, in design, and in evaluation of EFLX embedded FPGA for a wide range of applications and our IP Alliance membership will enable us to support them even better going forward.”

STMicroelectronics (NYSE: STM) has announced the integration of its contactless NFC technology with MediaTek’s mobile platforms. This creates a complete solution for handset developers to design next-generation smartphones capable of supporting tightly integrated NFC mobile services.

Mobile payments are expected to see triple-digit growth in the coming years, with contactless transport ticketing also rising fast in Asia, notably in China’s largest cities.

By integrating ST’s NFC chipset with the MediaTek mobile platforms, the two partners help mobile OEMs overcome key technical challenges such as antenna design and integration, antenna miniaturization, and bill-of-material optimization while assuring interoperability with payment terminals in locations like retailers and transportation hubs.

MediaTek is the world’s second-largest supplier of mobile-handset solutions, and with the addition of ST’s technology can demonstrate high contactless performance relative to alternative platforms.

“ST will provide its NFC technology to MediaTek, to deliver high contactless performance solutions to OEMs with a focus on cost and integration optimization through smaller antennas and reduced bill of materials,” said Marie-France Florentin, Group Vice President, General Manager, Secure Microcontroller Division, STMicroelectronics. “While ST has for years been providing to customers its own robust NFC and RFID technology, the ST21NFCD is the first device from ST to integrate the market-proven booster technology ST recently acquired.”

About ST’s Mobile-Transaction (NFC) Technology:

Mobile payments and other contactless applications are primarily enabled by Near-Field Communication (NFC) technology, as found in contactless-payment cards and payment terminals. ST’s NFC chipset, or System-in-Package, solves the challenges of achieving a robust wireless connection over extended communication distances to make mobile payments easy, dependable, and private, while protecting against cybersecurity threats including eavesdropping and hacking.

ST’s latest NFC Systems-in-Package ST54F and ST54H comprise the ST21NFCD NFC controller with active load modulation for extended range with ST33G1M2 and ST33J2M0 embedded secure element (eSE), and operating system.

 

Toshiba Corporation (TOKYO:6502) (Toshiba) is in continuing negotiations with three consortia of potential purchasers of Toshiba Memory Corporation (TMC): the Innovation Network Corporation of Japan, Bain Capital Private Equity LP and Development Bank of Japan consortium; a consortium that includes Western Digital; and a consortium that includes Hon Hai. At this point, Toshiba has not made any decision to reduce the pool of candidate purchasers of TMC.

There have been media reports speculating that Toshiba will make a decision on Aug 31 at Toshiba’s Board of Directors meeting. While Toshiba exercised its best efforts to reach a mutually satisfactory definitive agreement with one of the consortia seeking to purchase TMC, the negotiation with each consortium has not reached the point which will allow Toshiba’s Board of Directors could make a decision regarding the sale of TMC.

The memory business requires timely investments, accelerated product development, and the ability to quickly ramp-up large-scale production capacity; Highly reliable memory devices are essential to meet growing demand for storage. Accordingly, Toshiba is looking for a purchaser of TMC that is able to deliver flexible, rapid decision-making and enhanced financial options, and to promote further growth of TMC’s memory business, while also being capable of contributing enough value from the sale of TMC to return the Toshiba group to positive equity.

Toshiba intends to continue negotiations with possible bidders to reach a definitive agreement which meets Toshiba’s objectives at the earliest possible date, and will announce material changes in status in a timely manner.

To perpetuate the pace of innovation and progress in microelectronics technology over the past half-century, it will take an enormous village rife with innovators. This week, about 100 of those innovators throughout the broader technology ecosystem, including participants from the military, commercial, and academic sectors, gathered at DARPA headquarters at the kickoff meeting for the Agency’s new CHIPS program, known in long form as the Common Heterogeneous Integration and Intellectual Property (IP) Reuse Strategies program.

Many future microelectronics systems could be assembled with a library of plug-and-play chiplets that combine their respective modular functions with unprecedented versatility.

Many future microelectronics systems could be assembled with a library of plug-and-play chiplets that combine their respective modular functions with unprecedented versatility.

“Now we are moving beyond pretty pictures and mere words, and we are rolling up our sleeves to do the hard work it will take to change the way we think about, design, and build our microelectronic systems,” said Dan Green, the CHIPS program manager. The crux of the program is to develop a new technological framework in which different functionalities and blocks of intellectual property—among them data storage, computation, signal processing, and managing the form and flow of data—can be segregated into small chiplets, which then can be mixed, matched, and combined onto an interposer, somewhat like joining the pieces of a jigsaw puzzle. Conceivably an entire conventional circuit board with a variety of different but full-sized chips could be shrunk down onto a much smaller interposer hosting a huddle of yet far smaller chiplets.

Central to the design and intention of the program is the creation of a new community of researchers and technologists that mix-and-match mindsets, skillsets, technological strengths, and business interests. That is why the dozen selected prime contractors for the program include large defense companies (Lockheed Martin, Northrop Grumman, and Boeing), large microelectronics companies (Intel, Micron, and Cadence Design Systems), other semiconductor design players (Synopsys, Intrinsix Corp., and Jariet Technologies), and university teams (University of Michigan, Georgia Institute of Technology, and North Carolina State University). What’s more, many of these prime contractors will be working with additional partners who will extend the village of innovators working on the CHIPS program.

“If the CHIPS program is successful, we will gain access to a wider variety of specialized blocks that we will be able to integrate into our systems more easily and with lower costs,” said Green. “This should be a win for both the commercial and defense sectors.”

Among the specific technologies that could emerge from this newly formed research community are compact replacements for entire circuit boards, ultrawideband radio frequency (RF) systems, which require tight integration of fast data converters with powerful processing functions, and, by combining chiplets that provide different accelerator and processor functions, fast-learning systems for teasing out interesting and actionable data from much larger volumes of mundane data. “By bringing the best design capabilities, reconfigurable circuit fabrics, and accelerators from the commercial domain, we should be able to create defense systems just by adding smaller specialized chiplets,” said Bill Chappell, director of DARPA’s Microsystems Technology Office.

“The CHIPS program is part of DARPA’s much larger effort, the Electronics Resurgence Initiative, in which we are striving to build an electronics community that mixes the best of the commercial and defense capabilities for national defense,” Chappell said. “The ERI, which will involve roughly $200 million annual investments for the next four years, will nurture research in materials, device designs, and circuit and system architecture. The next round of investments are expected this September as part of the broader initiative.”

The ConFab – an exclusive conference and networking event for semiconductor manufacturing and design executives from leading device makers, OEMs, OSATs, fabs, suppliers and fabless/design companies – announces the 2018 event will be held at THE COSMOPOLITAN of LAS VEGAS on May 20-23.

Pete Singer, Conference Chair of The ConFab and Editor-in-Chief of Solid State Technology had this to say, “The ConFab is a unique combination of business, technology and social interactions that make this industry gathering of influencers and leaders so valuable. In 2018, we will take a close look at the new applications driving the semiconductor industry, the technology that will be required at the device and process level to meet new demands, and – perhaps most importantly – the kind of strategic collaboration that will be required.” He also stated, “the key to continued business success for both guests and presenters will be the crucial insights that will be gained at the conference about critical market trends; and how to take advantage of emerging opportunities. Our goal is to “connect the dots” and how what’s going on in the end semiconductor application space (IoT, AI, 5G, VR, automotive, etc.) will ultimately impact semiconductor manufacturing and design.”

Keynotes, panel discussions and technical sessions on new technology needed in manufacturing will be a focal point of The ConFab 2018. Topics include: EUV, now entering volume production and ushering in a new era of patterning for the 7 and 5nm generations. And the many new materials being considered, transistors that are evolving from FinFETs to gate-all-around nanowires, on chip communication with silicon photonics emerging, and advanced packaging/heterogeneous integration as ever more critical. How semiconductors are playing an increasingly important role in the healthcare industry, will also be in the robust 2018 agenda.

The ConFab is a high-level, 3 1/2 day conference for decision-makers and influencers to connect, innovate and collaborate in multiple sessions, one-on-one private business meetings, and other daily networking activities. For more information, visit www.theconfab.com.