Category Archives: 3D Integration

Laser debonding for ultrathin and stacked fan out packages

July 27, 2017

BY ELISABETH BRANDL, THOMAS UHRMANN and MARTIN EIBELHUBER, EV Group, St. Florian, Austria

Fan-out packaging is an established technology for many mobile applications. Whereas early semiconductor packages have been single-chip packages, the continuing trend of expanding the wiring surface to support increased functionality has led to more complex packages, stacked packages, systems inpackageaswellashigh-performancepackages. With this development, fan-out technology is bridging a gap between cost-competitive packaging and high performance. For all aforementioned packages, temporary bonding will be needed, either to enable the thinning of wafers to address the need for smaller form factors, to achieve cost savings on mold materials or to serve as a processing platform for redistribution-layer (RDL) first processes.

Temporary bonding requires both a bonding and debonding process. Determining the right debonding technology can be difficult and confusing as every application from fan-out wafer-level packaging (FoWLP) to power devices has its own requirements in terms of process temperature, mechanical stress and thermal budget, to name just a few considerations. In this article, we will focus on laser debonding, where high- temperature compatible materials are available. We will point out for which applications the laser debond characteristics fit well.

To limit the thermal input associated with debonding, UV lasers are utilized for debonding where several materials from different temporary bonding material suppliers are available. To confine the maintenance effort to a minimum, a diode-pumped solid-state (DPSS) laser is the right choice in combination with beam-shaping optics for high process control and minimum heat input.

Challenges of temporary bonding for FoWLP

FoWLP has gained significant industry interest in part due to carrier, the requirements of the temporary bonding material in terms of chemical and thermal compat- ibility are high. Certain kinds of polyimides comply with this harsh environment and are also suitable for laser debonding.

By just comparing these two processes, the require- ments differ significantly even though both are FoWLP processes. By looking at the wide variety of semiconductor processes for various applications, it becomes clear that no single debonding process solution is compatible with all semiconductor processes, but rather several solutions are necessary. This is the reason why a variety of debonding processes (temporary bonding is characterized by the debonding technology) have been developed and are still in use today.

Comparison of the mainstream debonding technologies

The most common debonding methods are thermal slide-off debonding, mechanical debonding and UV laser debonding. These three methods are all in high- volume manufacturing and differ strongly in their process compatibility.

Thermal slide-off is a method that employs a thermo-plastic material as an adhesive interlayer between the device and carrier wafer. The debonding method uses the reversible thermal behavior of the thermoplastic material, meaning that at elevated temperatures the material experiences a drop in viscosity, which enables debonding to be accomplished by simply sliding the wafers off of each other. The character- istics of thermal slide-off debonding is bonding and debonding at elevated temperatures, which depending on the thermoplastic material being used can range between 130 and 350°C. Temperature stability depends in large part on mechanical stress, which can be observed due to the thermoplastic’s low viscosity at high temperatures [1].

Mechanical debonding is a method that is highly dependent on the surface properties of the wafers involved as well as the adhesion and cohesion of the temporary bonding material. For most material systems, a mechanical release layer is applied to achieve a controlled debonding mechanism. Key characteristics of mechanical debonding include processing at room temperature and a strong dependence on mechanical stress. Since mechanical debonding needs a low adhesion between the temporary bonding material and the wafer for a successful debond process, it can be tricky to use it for FoWLP applications. This is because the high wafer stress associated with FoWLP processing can lead to spontaneous debonding, even during the thinning process, which in turn can result in a drastic drop in yield [2].

Laser debonding is a technology that has been implemented with several different variations. The debond mechanism depends on the type of laser as well as the temporary bonding adhesive or the specific release layer used for the process. Infrared lasers work on the principle of the photo thermal process, where light is absorbed and transferred into heat, which leads to high temperatures within the bond interface. UV laser debonding typically uses the photo chemical process, where light is absorbed and the energy is used for breaking chemical bonds. Breaking the chemical bonds of a polymer results in the production of fragments of the original polymer. These fragments comprise gases, which increase the pressure within the interface to support the debonding process. For FoWLP applications, this method is a good fit due to the high adhesion of the temporary bonding adhesive to the wafers before the debonding process.

Optimized solution for FoWLP applications

UV lasers are advantageous for FoWLP processing due to their limited thermal input through the debonding process. The carrier wafer must be transparent to the UV laser’s wavelength to ensure efficient use of the laser energy and also ensure a higher lifetime of the carrier wafer. Two main types of UV lasers are available (solid-state laser and excimer laser), with each having several different wavelength options. Choosing a laser with a wavelength larger than 300nm is optimal for several reasons. First, commercially available laser debond materials effectively absorb and therefore debond at wavelengths higher than 300nm. Second, it allows a standard glass wafer to be used as the carrier since glass enables high transmission in this wavelength regime.

Solid-state lasers have the advantage of lower maintenance costs because they do not need halogen gas, which must be replaced on a regular basis. For solid-state lasers, the consumables are very low, and depending on the amount of power used by the laser there are examples of lasers used for laser debonding on a 24/7 basis that have required no laser consumables in the first five years of operation. Additionally, a smaller footprint can also be achieved due to a compact optical setup. Solid-state lasers typically have Gaussian beam profiles, pictured in FIGURE 3.

UV laser debonding is a threshold process, meaning that debonding occurs above a certain value of radiant exposure. In Figure 3, the area with the blue criss-cross lines indicates the radiant exposure, which is used for the debonding process. The energy that is below or above that value (areas in red in the picture) cannot be used for debonding and is typically trans- ferred into heat, which can lead to carbonization and particle creation. Because of the lack of sufficient energy at the edge of the Gaussian laser beam profile, a certain overlap of the pulses is necessary, which is an additional variable that must be optimized in order to achieve successful debonding without carbonization. Additionally, the excess energy in the beam center can cause carbonization. A Gaussian beam profile is not suitable to limit thermal effects during debonding.

Gaussian beam profiles can be transferred into quasi top hat beam profiles by using a proprietary optical setup for beam shaping. By employing this optical setup, a highly reproducible beam for debonding (whereby the beam shape does not change over time) is achieved with constrained thermal input similar to what is seen in the “top hat” beam profile in FIGURE 4. This gives tighter process control, which in combination with the high pulse repetition rate of this laser type and the ability to scan across the surface of a fixed wafer leads to a well-controlled, high-throughput debonding process. The scanning process is pictured in FIGURE 5 where — in contrast to an excimer laser — the wafer is fixed on a static stage and the laser spot is controlled by a galvo scanner over the wafer. leads to a well-controlled, high-throughput debonding process.

As shown in FIGURE 6, a test wafer is used to determine the optimum radiant exposure for debonding. Even with a top hat beam profile, it is important to use a radiant exposure value close to the debonding threshold to minimize heat effects [3]. Small overlaps are necessary nonetheless because the adhesion between the temporary bonding material and the wafers is very high.

Temporary bonding for future FoWLP

Ultrathin and stacked fan-out packages, also called Package on package (PoP), are already on several industry roadmaps due to their ability to enable higher device densities. However, the need for reconstituted wafers to become even thinner for PoP versus current FoWLP will give rise to more challenges for temporary bonding. For example, the bow of the temporary bonded wafer stack consisting of a molded wafer and a carrier wafer must be minimized to ensure uniform thinning. The maximum total thickness variation (TTV) will also become tighter depending on the final thickness. As for every 3D application, questions regarding interconnects, such as choosing via first or via last, also arises for PoP, where several processes are also available and where no standard process exists that is employed by all fan-out packaging houses.

Summary

UV laser debonding is a suitable method for both chip- first and chip-last/RDL-first FoWLP processes because it offers debonding at room temperature, and because chemically stable materials are available. The UV laser debonding solutions presented in this article combine the advantages of the solid-state laser with low mainte- nance, low consumables costs and high pulse frequencies combined with high spatial control due to the special beam-shaping optics.

Further Readings

1. Critical process parameters and failure analysis for temporary bonded wafer stacks. Karine Abadie, Elisabeth Brandl, Frank Fournel, Pierre Montméa, Wimplinger, Jürgen Burggraf, Thomas Uhrmann, Julian Bravin. Fountain Hills, Arizona: iMaps, 2016. iMaps Device Packaging Conference.

2. Temporary Wafer Carrier Solutions for thin FOWLP and eWLB-based PoP. Jose Campos, André Cardoso, Mariana Pires, Eoin O’Toole, Raquel Pinto, Steffen Kröhnert, Emilie Jolivet, Thomas Uhrmann, Elizabeth Brandl, Jürgen Burggraf, Harald Wiesbauer, Julian Bravin, Markus Wimplinger and Paul Lindner. San Jose, California : SMTA International, 2015. iWLPC (International Wafer Level Packaging Conference).

3. Key Criteria for Successful Integration of Laser Debonding. Elisabeth Brandl, Thomas Uhrmann, Jürgen Burggraf, Martin Eibelhuber, Harald Wiesbauer, Mariana Pires, Philipp Kolmhofer, Matthias Pichler, Julian Bravin, Markus Wimplinger and Paul Lindner. San Jose, California : SMTA Inter- national, 2016. iWLPC.

Gartner reports worldwide PC shipments declined 4.3% in second quarter of 2017

July 21, 2017

Worldwide PC shipments totaled 61.1 million units in the second quarter of 2017, a 4.3 percent decline from the second quarter of 2016, according to preliminary results by Gartner, Inc. The PC industry is in the midst of a 5 year slump, and this is the 11th straight quarter of declining shipments. Shipments in the second quarter of this year were the lowest quarter volume since 2007.

“Higher PC prices due to the impact of component shortages for DRAM, solid state drives (SSDs) and LCD panels had a pronounced negative impact on PC demand in the second quarter of 2017,” said Mikako Kitagawa, principal analyst at Gartner “The approach to higher component costs varied by vendor. Some decided to absorb the component price hike without raising the final price of their devices, while other vendors transferred the costs to the end-user price.”

However, in the business segment, vendors could not increase the price too quickly, especially in large enterprises where the price is typically locked in based on the contract, which often run through the quarter or even the year,” Ms. Kitagawa said. “In the consumer market, the price hike has a greater impact as buying habits are more sensitive to price increases. Many consumers are willing to postpone their purchases until the price pressure eases.”

HP Inc. reclaimed the top position from Lenovo in the worldwide PC market in the second quarter of 2017 (see Table 1). HP Inc. has achieved five consecutive quarters of year-over-year growth. Shipments grew in most regions, and it did especially well in the U.S. market where its shipments growth far exceeded the regional average.

Table 1
Preliminary Worldwide PC Vendor Unit Shipment Estimates for 2Q17 (Thousands of Units)

Company	2Q17 Shipments	2Q17 Market Share (%)	2Q16 Shipments	2Q16 Market Share (%)	2Q17-2Q16 Growth (%)
HP Inc.	12,690	20.8	12,285	19.2	3.3
Lenovo	12,188	19.9	13,305	20.8	-8.4
Dell	9,557	15.6	9,421	14.7	1.4
Apple	4,236	6.9	4,252	6.7	-0.4
Asus	4,036	6.6	4,501	7.0	-10.3
Acer Group	3,850	6.3	4,402	6.9	-12.5
Others	14,546	23.8	15,710	24.6	-7.4
Total	61,105	100.0	63,876	100.0	-4.3

Notes: Data includes desk-based PCs, notebook PCs and ultramobile premiums (such as Microsoft Surface), but not Chromebooks or iPads. All data is estimated based on a preliminary study. Final estimates will be subject to change. The statistics are based on shipments selling into channels. Numbers may not add up to totals shown due to rounding.
Source: Gartner (July 2017)

Lenovo’s global shipments declined 8.4 percent in the second quarter of 2017, after two quarters of growth. Lenovo recorded year-over-year shipment declines in all key regions. Ms. Kitagawa said the 2Q17 results could reflect Lenovo’s strategic shift from unit share gains to margin protection. The strategic balance between share gain and profitability is a challenge for all PC vendors.

Dell achieved five consecutive quarters of year-on-year global shipment growth, as shipments increased 1.4 percent in 2Q17. Dell has put a high priority on PCs as a strategic business. Among the top three vendors, Dell is the only vendor which can supply the integrated IT needs to businesses under the Dell Technologies umbrella of companies.

In the U.S., PC shipments totaled 14 million units in the second quarter of 2017, a 5.7 percent decline from the second quarter of 2016 (see Table 2). The U.S. market declined due to weak consumer PC demand. The business market has shown some consistent growth, while early indicators suggest that spending in the public sector was on track with normal seasonality as the second quarter is typically the peak PC procurement season. However, the education market was under pressure from strong Chromebook demand.

The Chromebook market has been growing much faster than the overall PC market. Gartner does not include Chromebook shipments within the overall PC market, but it is moderately impacting the PC market. Worldwide Chromebook shipments grew 38 percent in 2016, while the overall PC market declined 6 percent.

“The Chromebook is not a PC replacement as of now, but it could be potentially transformed as a PC replacement if a few conditions are met going forward,” Ms. Kitagawa said. “For example, infrastructure of general connectivity needs to improve; mobile data connectivity needs to become more affordable; and it needs to have more offline capability.”

Table 2
Preliminary U.S. PC Vendor Unit Shipment Estimates for 2Q17 (Thousands of Units)

Company	2Q17 Shipments	2Q17 Market Share (%)	2Q16 Shipments	2Q16 Market Share (%)	2Q17-2Q16 Growth (%)
HP Inc.	4,270	30.5	4,008	27.0	6.5
Dell	3,874	27.7	3,801	25.6	1.9
Lenovo	1,848	13.2	2,207	14.9	-16.3
Apple	1,649	11.8	1,825	12.3	-9.6
Asus	447	3.2	754	5.1	-40.7
Others	1,921	13.7	2,257	15.2	-14.9
Total	14,009	100.0	14,852	100.0	-5.7

PC shipments in EMEA totaled 17 million units in the second quarter of 2017, a 3.5 percent decline year over year. There were mixed results across various countries. Uncertainty around the U.K. elections meant some U.K. businesses delayed buying, especially in the public sector. In France, consumer confidence rose more than expected after Emmanuel Macron was elected president, however spending on PCs remains sluggish. PC shipments increased in Germany as businesses invest in Windows 10 based new hardware, and the Russian market continued to show improvement driven by economic stabilization.

In Asia/Pacific, PC shipments surpassed 21.5 million units in the second quarter of 2017, down 5.1 percent from the same period last year. The PC market in this region was primarily affected by market dynamics in India and China. In India, the pent up demand after the demonetization cooled down after the first quarter, coupled with the absence of a large tender deal compared to a year ago and higher PC prices, brought about weak market growth. The China market was hugely impacted by the rise in PC prices due to the component shortage

These results are preliminary. Final statistics will be available soon to clients of Gartner’s PC Quarterly Statistics Worldwide by Region program. This program offers a comprehensive and timely picture of the worldwide PC market, allowing product planning, distribution, marketing and sales organizations to keep abreast of key issues and their future implications around the globe.

2017 IEEE IEDM to showcase technology and device breakthroughs in logic, memory, bioelectronics, silicon photonics

July 20, 2017

Advances in semiconductor and related devices are driving significant progress in our increasingly digital world, and the place to learn about cutting-edge research in the field is the annual IEEE International Electron Devices Meeting (IEDM), to be held December 2-6, 2017 at the Hilton San Francisco Union Square hotel. Highlights for 2017 include:

A talk on transformative electronics by Dr. Hiroshi Amano, who received the 2014 Nobel Prize in Physics along with Isamu Akasaki and Shuji Nakamura for the invention of efficient blue LEDs, which sparked a revolution in innovative, energy-saving lighting.
The above talk is part of an exceptional slate of plenary talks to be given by some of the industry’s leading figures. IEDM plenary presenters include the CEO of Advanced Micro Devices, Inc.; the research chief of TSMC, which is the industry’s largest foundry driving technology forward; a leading academic authority on energy-efficient computing, which is a key societal goal; as well as Dr. Amano’s fourth, additional plenary talk. It will be given on Wednesday, Dec. 6.
Focus Sessions will be held on the following topics: 3D Integration and Packaging; Modeling Challenges for Neuromorphic Computing; Nanosensors for Disease Diagnostics; and Silicon Photonics: Current status and perspectives.
A vendor exhibition will be held again, based on the success of last year’s first-ever such event at the IEDM.
The IEEE Magnetics Society will host a poster session on MRAM (magnetic RAM memories).

The IEDM paper submission deadline this year is August 2 and the deadline for late-news papers is September 11. Only a limited number of late-news papers will be accepted.

Each year at the IEDM, the world’s best technologists in micro/nano/bioelectronics converge to participate in a technical program consisting of more than 220 presentations along with special luncheon talks and a variety of panels, special sessions, tutorials, Short Courses, IEEE/EDS award presentations and other events that highlight leading work in more diverse areas of the field than any other conference.

“This year’s IEDM will feature talks, courses and panels by world experts on what is perhaps the broadest array of topics in recent memory,” said Dr. Barbara De Salvo, Scientific Director at Leti. “The unique technical program can lead one to view the IEDM as a crystal ball of sorts, because many of the developments reported at the conference invariably make their way into commercial products a few years down the road. As an example, this year’s IEDM conference marks 10 years since the industry transition from aluminum to copper interconnect began in earnest.”

Here are details of some of the events that will take place at this year’s IEDM:

Focus Sessions

3D Integration and Packaging – Packaging technology is taking on an increasingly important role in semiconductor manufacturing, and this session will provide an industry perspective on forthcoming approaches ranging from “Simpler is better” to “Advanced packaging saves the day for continued scaling.” The session will address the latest in 3D, from alternative packaging to 3D stacking, and applications and technologies for Integrated Power Microelectronics.
Modeling Challenges for Neuromorphic Computing – This session will address the opportunities and challenges of efficient synaptic processes, from learning models to device-circuit implementations of neuromorphic architectures. Half of the session will discuss learning models in stochastic processes, with the other half devoted to RRAM (resistive RAM) memory for deep neural networks and neuromorphic computing.
Nanosensors for Disease Diagnostics — From microfluidics to nanosensing, this session will review the latest advances for the detection of diseases such as cancer, sepsis and diabetes, using biomarkers ranging from (bio)molecules and individual cells to in-vitro tissue models.
Silicon Photonics: Current Status and Perspectives – This session addresses the state-of-the-art in silicon photonics technology, ranging from topics on high-volume manufacturing, optical transceivers and interconnects, to femto-joule per bit integrated nanophotonics for upcoming market applications in optical computing.

90-Minute Tutorials – Saturday, Dec. 2
A program of 90-minute tutorial sessions on emerging technologies will be presented by experts in the fields, bridging the gap between textbook-level knowledge and leading-edge current research. Advance registration is recommended.

The Evolution of Logic Transistors Toward Low Power and High Performance IoT Applications, Dr. Dae Won Ha, Samsung Electronics
Negative Capacitance Transistors, Prof. Sayeef Salahuddin, UC Berkeley
Fundamental, Thermal, and Energy Limits of PCM and ReRAM, Prof. Eric Pop, Stanford University
Hardware Opportunities in Cognitive Computing: Near- and Far-Term, Dr. Geoffrey Burr, Principal Research Staff Member, IBM Research-Almaden
2.5D Interposers and High-Density Fanout Packaging as Enablers for Future Systems Integration, Dr. Sundaram Venkatesh, Associate Director, Georgia Tech 3D Systems Packaging Research Center
Silicon Photonics for Next-Generation Optical Interconnects, Dr. Joris Van Campenhout, Program Director Optical I/O, IMEC

Short Courses – Sunday, Dec. 3
Short Courses provide the opportunity to learn about important areas and developments, and provide the opportunity to network with experts from around the world. Advance registration is recommended.

Performance Boosters and Variation Management in Sub-5nm CMOS, organized by Sandy Liao, Intel
Merged Memory-Logic Technologies and Their Applications, organized by Kevin Zhang, TSMC

Plenary Presentations – Monday, Dec. 4

System Scaling Innovation for Intelligent Ubiquitous Computing, Jack Sun, VP of R&D, TSMC
Driving the Future of High-Performance Computing, Lisa Su, President & CEO, AMD
Energy-Efficient Computing and Sensing: From Silicon to the Cloud, Adrian Ionescu, Professor, EPFL

Plenary Presentation – Wednesday, Dec. 6

Development of a Sustainable Smart Society by Transformative Electronics, Hiroshi Amano, Professor, Nagoya University

Evening Panel Session – Tuesday evening, Dec. 5
The IEDM offers attendees an evening session where panels of experts give their views on important industry topics. Audience participation is encouraged to foster an open and vigorous exchange of ideas.

Who Will Lead the Industry in the Future? Moderator: Prof. Philip Wong, Stanford University

Entrepreneurs Lunch
The topic and speaker are yet to be determined, but this popular luncheon jointly sponsored by IEDM and the IEEE Electron Devices Society will be held once again.

Further information about IEDM
For registration and other information, visit www.ieee-iedm.org.

Taiwan largest semiconductor materials market, as SEMICON Taiwan approaches

July 19, 2017

Taiwan is the world’s largest consumer of semiconductor materials for the seventh consecutive year, bringing new opportunities in this increasingly critical sector. SEMICON Taiwan (13-15 September), held at Taipei’s Nangang Exhibition Center, will feature over 1,700 booths and 700 exhibitors, and more than 45,000 attendees from the global electronics manufacturing supply chain. This year, in addition to the much-anticipated Executive Summit, themed “Transformation: A Key to Solution,” 27 international forums will be held, exploring major issues. Speakers from TSMC, UMC, Powerchip, NVIDIA, Micron and Amkor will share their insights on trends and strategies of the next-generation electronics industry.

According to the SEMI Material Market Data Report, Taiwan’s semiconductor materials consumption was US$9.8 billion in 2016 − the world’s largest. Global semiconductor manufacturing equipment billings reached US$13.1 billion in Q1 2017, exceeding the record quarterly high set in Q3 2000. These figures signal that application drivers will continue to drive the development of a supply chain feeding their manufacturing processes, equipment and materials.

“As SEMICON Taiwan celebrates its 22^nd year, the exhibition area will be expanded to closely align with the four major trends of applications in the market, which include Internet of Things (IoT), Smart Manufacturing, Smart Transportation, and Smart Medtech,” said Terry Tsao, president of SEMI Taiwan. “This year, SEMICON Taiwan aims to increasingly connect the entire manufacturing ecosystem vertically and horizontally. In addition, it will provide an overview of market trends and leading technologies in the industry, with forums and business matching activities which will enable collaboration and new opportunities.”

Theme Pavilions and Region Pavilions Focus on Opportunities

In addition to the eight customary theme pavilions, five new pavilions are featured this year, and to promote cross-border collaboration, eight regional pavilions are offered. The 21 pavilions include:

Theme Pavilions

Automated Optical Inspection (AOI)
Chemical Mechanical Planarization (CMP)
High-Tech Facility
Materials
Precision Machinery
Secondary Market
Smart Manufacturing & Automation
Taiwan Localization

New Theme Pavilions

Circular Economy
Compound Semiconductor
Flexible Hybrid Electronics/Micro-LED
Laser
Opto Semiconductor

Regional Pavilions

Cross-Strait
German
Holland High-Tech
Korean
Kyushu (Japan)
Okinawa (Japan)
Silicon Europe
Singapore

Co-located with SEMICON Taiwan 2017, the SiP Global Summit will discuss three key system-in-package topics:

Package Innovation in Automotive
3D IC, 3D interconnection for AI and High-end Computing
Innovative Embedded Substrate and Fan-Out Technology to Enable 3D-SiP Devices

Participants will share trends on 2.5D/3D IC technologies, and the evolution and challenges of embedded technologies and wafer level packaging.

This is the first year that the International Test Conference (ITC) will be co-located with SEMICON Taiwan 2017, also marking the first time that ITC is held in Asia. The conference will focus on the rapid growth of emerging applications like IoT and automotive electronics, and how testing technologies are challenged by rapid advancements of manufacturing processes, 3D stacking and SiP.

For more information about SEMICON Taiwan 2017, please visit www.semicontaiwan.org or follow us on Facebook.

2H17 DRAM, NAND ASP growth to cool, but yearly growth strong

July 18, 2017

In its upcoming Mid-Year Update to The McClean Report 2017 (to be released at the end of July), IC Insights addresses the amazing growth of the 2017 DRAM and NAND flash memory markets.

Sales of both memory types—DRAM and NAND—are expected to set record highs this year. In both cases, the strong annual upturn in sales is being driven almost entirely by fast-rising average selling prices. In the case of DRAM, unit shipments are actually forecast to show a decline this year. Moreover, NAND shipments are forecast to increase only 2%, providing a small, added boost to the market growth in that segment. Prices for DRAM and NAND first began increasing in the second half of 2016, and continued with quarterly increases through the first half of 2017. Figure 1 plots the robust quarterly ASP growth rates, which, from 3Q16 through 2Q17, averaged 16.8% for DRAM and 11.6% for NAND.

Figure 1

With DRAM ASPs surging since the third quarter of 2016, DRAM manufacturers once again stepped up their spending for this segment. However, the majority of this spending is going towards technology advancements and not toward capacity additions.

IC Insights believes that essentially all of the spending for flash memory in 2017 will be used for 3D NAND flash memory process technology as opposed to planar flash memory. A big increase in NAND flash capital spending this year is expected from Samsung as it ramps 3D NAND production at its large, new fab in Pyeongtaek, South Korea.

Historical precedent in the memory market shows that too much spending usually leads to overcapacity and subsequent pricing weakness. Samsung, SK Hynix, Micron, Intel, Toshiba/SanDisk, and XMC/Yangtze River Storage Technology each plan to significantly ramp up 3D NAND flash capacity over the next couple of years (with additional new Chinese producers possibly entering the market). The likelihood of overshooting 3D NAND flash capacity over the next few years is very high.

IC Insights shows the DRAM quarterly ASP growth rate peaked in 4Q16 but continued a strong upward trend through 2Q17. IC Insights forecasts the DRAM ASP to increase (though marginally) into 3Q17 before edging slightly negative in 4Q17, signaling the end of another cyclical upturn.

Even though DRAM ASP growth is forecast to slow in the second half of the year, the annual DRAM ASP growth rate is still forecast to be 63%, which would be the largest annual rise for DRAM ASPs dating back to 1993 when IC Insights first started tracking this data. The previous record-high annual growth rate for DRAM ASP was 57% in 1997. For NAND flash, the 2017 ASP is forecast to increase 33%, also a record high gain. (In the year 2000, the predominantly NOR-based flash ASP jumped 52%).

The 250+ page Mid-Year Update to the 2017 edition of The McClean Report further describes IC Insights’ updated forecasts for DRAM and NAND flash memory for 2017-2021 and includes a refreshed outlook on its semiconductor capital expenditure forecast.

Hamburg researchers develop new transistor concept

July 17, 2017

Transistors, as used in billions on every computer chip, are nowadays based on semiconductor-type materials, usually silicon. As the demands for computer chips in laptops, tablets and smartphones continue to rise, new possibilities are being sought out to fabricate them inexpensively, energy-saving and flexibly. The group led by Dr. Christian Klinke has now succeeded in producing transistors based on a completely different principle. They use metal nanoparticles which are so small that they no longer show their metallic character under current flow but exhibit an energy gap caused by the Coulomb repulsion of the electrons among one another. Via a controlling voltage, this gap can be shifted energetically and the current can thus be switched on and off as desired. In contrast to previous similar approaches, the nanoparticles are not deposited as individual structures, rendering the production very complex and the properties of the corresponding components unreliable, but, instead, they are deposited as thin films with a height of only one layer of nanoparticles. Employing this method, the electrical characteristics of the devices become adjustable and almost identical.

These Coulomb transistors have three main advantages that make them interesting for commercial applications: The synthesis of metal nanoparticles by colloidal chemistry is very well controllable and scalable. It provides very small nanocrystals that can be stored in solvents and are easy to process. The Langmuir-Blodgett deposition method provides high-quality monolayered films and can also be implemented on an industrial scale. Therefore, this approach enables the use of standard lithography methods for the design of the components and the integration into electrical circuits, which renders the devices inexpensive, flexible, and industry-compatible. The resulting transistors show a switching behavior of more than 90% and function up to room temperature. As a result, inexpensive transistors and computer chips with lower power consumption are possible in the future. The research results have now been published in the scientific journal “Science Advances“.

“Scientifically interesting is that the metal particles inherit semiconductor-like properties due to their small size. Of course, there is still a lot of research to be done, but our work shows that there are alternatives to traditional transistor concepts that can be used in the future in various fields of application”, says Christian Klinke. “The devices developed in our group can not only be used as transistors, but they are also very interesting as chemical sensors because the interstices between the nanoparticles, which act as so-called tunnel barriers, react highly sensitive to chemical deposits.”

PLAT4M matures three silicon photonic platforms

July 14, 2017

Leti today announced that the European FP7 project PLAT4M has now been completed with results that exceeded expectations.

Si photonics has long been expected to bring substantial breakthroughs in very high speed data communications, telecommunications and supercomputing. In addition, it is one of the most promising industrial-production candidates because of its potential for large-scale and low-cost production capability in existing CMOS foundries.

The European Commission launched the 15-member PLAT4M project in 2012 to build a Si photonics supply chain in Europe that would speed industrialization of the technology by enabling its seamless transition to commercial production.

The main objective of PLAT4M was to advance existing silicon photonics research foundries and seamlessly transition to pilot line operation and industrial manufacturing of products based on silicon photonics. The supply chain is based on three different but complementary technology platforms of Leti, STMicroelectronics and imec.

Leti Platform

Leti’s 8,500m2 cleanroom facility includes a 200mm pilot line that enables fabrication of passives, detectors, modulators and integrated lasers with a focus on high-bandwidth devices. The project team developed a new Si-photonic platform based on a 310nm silicon film on top of an 800nm buried oxide (BOX) on a high-resistivity silicon substrate. Since the targeted applications for the project were O-band transceivers and receivers, most of the developed devices are suitable for 1310nm operations.

CEA-LETI has developed 3 PDKs which are dedicated to Multi Project Wafers (MPW) runs on this silicon photonics technology which is now offered via the brokers CMP and Europractice. Moreover, III-V Lab has designed and co-fabricated a state-of-the-art integrated hybrid III-V/Si transmitter using a wafer bonding technique on this platform.

STMicroelectronics Platform

STMicroelectronics, the first 300mm wafer silicon photonics device manufacturer, is a key solution provider for 100 Gbps transceiver products since 2016. In parallel to its industrial activity, during the PLAT4M project ST developed another silicon photonics technology aimed at generating and nurturing further application specific industrial nodes. This technology platform creates an advanced photonic nanoscale environment, and combines state-of-the-art CMOS foundry tools with the flexibility necessary to support R&D efforts. Strong collaboration with research partners such as CEA LETI and University Paris Sud have been devoted to advanced studies in power consumption management, optical excess loss reduction and higher data-rate transmissions using complex modulation formats, signal multiplexing and higher Baud-rate devices. With R&D exploration that goes as far as core-to-core optical interposers, ST has also evaluated notions of device and circuit footprints toward Large System Integration (LSI).

In the context of PLAT4M, the participants chose a 4×25G transceiver as a Wavelength Division Multiplexing (WDM) data-communication demonstrator to validate both LETI and ST R&D platforms. The device functionalities were evaluated for compatibility with the 100GBase-LR4 standard, implying a signal transmission over 4 channels, spaced by 800 GHz around 1310 nm window, one fiber out and one fiber in.

imec Platform

In the course of the PLAT4M project imec has consolidated and further developed its silicon photonics technology platform ISIPP25G using its 200mm pilot line facilities located in Leuven to support industrial prototyping for various applications and markets. The imec platform component portfolio has been expanded to specific devices for sensing and high power free space applications. Furthermore, imec’s technology is supporting state-of-the-art modulation and detection at 50Gb/s and beyond with a variety of modulator options (GeSi EAM, Si MZM, Si MRM) now offered under its ISIPP50G technology along with both edge and surface fiber coupling technology and a library of O-Band and C-Band high quality passive components.

The technology is accessible through imec’s PDK, which is supported by software tools from several vendors including project partner PhoeniX Software. In collaboration with Mentor, a Siemens business, imec has also explored LVS verifications to reduce design errors and performed litho-friendly design analysis to improve the patterning predictability. Using the imec technology with new processing steps, TNO has demonstrated a multi-channel ring resonator based sensor system. Polytec demonstrated the operation of Multichannel Laser Doppler Vibrometer. THALES has demonstrated an integrated FMCW LiDAR system with 8 switchable output channels, enabling to scanning directions as well as a coherent beam combiner with 16 beams with linear operation up to a maximum input power of 26dBm. The thermal phase-shifter elements achieved a power efficiency of 10mW for a p-phase shift.

Finally, imec has demonstrated new advances in its technology such as a very low loss silicon waveguide technology (~0.6dB/cm for a 220nmx450nm waveguide) applying leading edge CMOS patterning technology developed in its 300mm pilot line with immersion lithography. It has also demonstrated a further reduction of thermal phase-shifter elements down to 4mW for a p-phase shift.

In an Unified Design Environment

The PLAT4M project has led to a qualitative leap of the design flow for silicon photonics, allowing the photonics community to design more complex and more robust circuits. Mentor and PhoeniX Software have worked closely together on an integrated electronics/photonics co-design workflow. This has been accomplished by building on existing tool-sets wherever possible and developing new technologies when required.

The supply chain includes EDA solutions such as Mentor’s Pyxis™ and Calibre®, which were extended to “understand” photonics. Interfaces were developed between these tools and Photonic IC design solution OptoDesigner from PhoeniX Software to create integrated design flows using the best practices from both photonics and electronics design. In addition, process design kit elements were developed for Mentor’s Calibre DRC, Calibre LVS, and Pyxis tools, incorporating new components, added models and fabrication information.

Producing a Packaging toolkit

Packaging played a key role in the development of the project demonstrators. The skills and processes developed by Aifotec and Tyndall, advanced the development of the Silicon Photonic packaging toolkit. This toolkit establishes standardised packaging processes for optical fibres, active devices, electronic components and thermo-mechanical systems to ensure that PICs can be more easily packaged in a timely and cost-effective way. A design rule document was made available through EuroPractice by Tyndall and also implemented into PDKs for OptoDesigner.

Perspectives

“The consortium developed advanced technologies and tools by building a coherent design flow, demonstrating manufacturability of elementary devices and process integration, and developing a packaging toolkit,” said Jean-Marc Fedeli, coordinator of the PLAT4M project. “The high level of maturity of the technology offered by these platforms makes them readily accessible to a broad circle of users in a fabless model.”

How low can we go?

July 11, 2017

By Ed Korczynski

In the advanced CMOS technology programs ongoing in the Belgium city of Leuven, imec works to extend the building-blocks of integrated circuits (IC). On the day before the opening of SEMICON West 2017, the invitation-only imec Technology Forum provided an update on the emerging opportunities in semiconductor technology and smart electronics systems. An Steegen, Executive VP Semiconductor Technology & Systems, provided the update on how small we can scale CMOS devices over the next 5-10 years. Taller finFETs will likely be used along with nano-wire FETs (NW-FET) by industry, and researchers see ways to cost-effectively combine both in future optimized System-on-Chips (SoC).

“Existing finFET technology can scale to the 5nm-node,” explained An Steegen at ITF 2017 in Antwerp, Belgium. “However, at the 3nm-node it looks like the nano-wire is comparable in performance to the finFET, but it has an additional advantage in that the nanowire is a better electro-statically controlled device so it enables gate-length scaling more than the finFET. So the contacted gate pitch (CGP) of a nano-wire can scale further than a finFET, because below ~40 nm CGP a finFET loses electro-static control which a nano-wire does not.”

While it is given that a nanowire has better electro-static control compared to a finFET, the basic trade-off is that of reduced drive current. The Figure shows that IMEC sees the possibility of System-Technology Co-Optimization (STCO) of future system-on-chip (SoC) designs using hybrid semiconductor technologies. imec’s basic process flow for NW-FETs starts with forming fins and so could be relatively easily integrated with finFETs for co-integrated hybrid CMOS.

System-Technology Co-Optimization (STCO) for future System-on-Chip (SoC) designs could integrate finFETs with Nano-Wire FETs (NW-FET) and Magnetic Random Access Memory (MRAM) for optimized performance. (Source: imec)

“Today, this SoC is processed in one technology which means it’s sub-optimal for certain blocks on the SoC,” explained Steegen. “So imagine a future where you can choose the preferred technology for each block. I would choose finFETs for those blocks that need drive current, while I would choose nano-wire-FETs for those blocks that need more density and lower power. I would for example choose a magnetic RAM to replace my cache memory. I can optimize each sub-block for a preferred technology. Now I can do more, like sprinkle in low-energy devices like tunnel-FETs or spin-devices or 2D-materials as low-energy switches.”

Super-vias and Rutherails

Design-Technology Co-Optimization (DTCO) is imec’s term for new interconnect technologies to allow for simpler or more-compact designs. IDTCO process-scaling boosters are needed to stay with the pace of aggressive design rule targets. “We’re working on super-vias that connect more than one metal to the other and can jump a number of levels, and buried rails to support finFETs in standard-cell libraries,” explained Steegen during ITF2017.

Super-vias could be cobalt plugs that connect more than two metal levels within on-chip multi-level interconnects. The cobalt plugs would be nominally 20nm diameter and 105nm deep, and connected to a dual-damscene upper metal line. Low-k dielectric of k=2.55 uses thin silicon carbon nitride (SiCN) for definition between the damascene levels.

Ruthenium rails (Rutherails) would be buried in a front-end dielectric layer to provide electrical contacts below finFETs for 42nm CGP and 21nm MP needed for imec 3nm-Node (I3N) devices. Ruthenium rails 30nm deep and 10nm wide do not need complex barrier layers and should provide sufficient current flow for either finFETs or NW-FETs.

imec is also working on materials R&D to extend the performance of 3D-NAND. Steegen said,

“At imec we are working on improving the performance of that Flash device by introducing high-mobility channels, also by engineering the dielectric trapping layer with a barrier that can help improve the erase window and also the retention.”

Leti and Fraunhofer team up to strengthen microelectronics innovation in France and Germany

June 29, 2017

Two European research institutes today announced their new collaboration to develop innovative, next-generation microelectronics technologies to spur innovation in their countries and strengthen European strategic and economic sovereignty.

Leti, a research institute of CEA Tech in Grenoble, France, and the Berlin-based Fraunhofer Group for Microelectronics, Europe’s largest R&D provider of smart systems, will initially focus on extending CMOS and More-than-Moore technologies to enable next-generation components for applications in the Internet of Things, augmented reality, automotive, health, aeronautics and other sectors, as well as systems to support French and German industries.

The agreement was signed today by Leti CEO Marie Semaria and Fraunhofer Group for Microelectronics Chairman Hubert Lakner during Leti Innovation Days, which are marking Leti’s 50^th anniversary.

“The ability to, one, develop key enabling technologies that overcome the formidable technical challenges that our leading technology companies will face, and, two, transfer them quickly to industry, is an essential focus for research institutes and industrials in France and Germany,” Semaria said. “Building on our previous, successful collaborations, Leti and the Fraunhofer Group for Microelectronics will bring our complementary strengths to the task of keeping France and Germany’s microelectronics industries in the forefront – and offer our innovations across Europe.”

“Micro-/nanoelectronics and smart systems are key enabling technologies for the economic success of Europe, especially in France and Germany. Thus, Europe can no longer afford to scatter its research competences. For the benefit of industry, joining forces will become more and more important, not only for industry but also for RTOs,” Lakner explained. “The new cooperation agreement will be the starting point for a strategic research cooperation of the two countries in order to jointly support the upcoming EC initiative, Important Project of Common European Interest (IPCEI), on micro- and nanoelectronics.”

Specific R&D projects that the collaboration will focus on include:

o Silicon-based technologies for next-generation CMOS processes and products, including design, simulation, unit process and material development as well as production techniques

o Extended More than Moore technologies for sensing and communication applications

o Advanced-packaging technologies.

The second phase of the collaboration may be expanded with additional academic partners and other countries, as needed.

Itâs time for new innovation

June 20, 2017

BY PETE SINGER, Editor-in-Chief

What if the automotive industry had achieved the incredible pace of innovation as the semiconductor industry during the last 52 years? A Rolls Royce would cost only $40, go around the world eight times on a gallon of gas, and have a top speed of 2.4 million miles per hour.

That point was made by Subi Kengeri speaking at The ConFab in May. Kengeri is vice president, CMOS Business Unit, at GlobalFoundries. He also noted that if one of today’s high performance graphics chips were produced using 1960 vs state-of-the-art “it would be the size of a football field.”

Clearly, no other industry can match the pace of innovation of the semiconductor industry. “The transistor count per square inch in 1965 was roughly 100. In 52 years, if you follow Moore’s Law of 2 years per innovation cycle, that gives 26 innovation cycles. That’s 100 millionX improvement (2X26),” Kengeri noted.

Of course, there has been plenty of innovation in the automotive industry. Interestingly, most of the exciting new innovations such as backup cameras, collision avoidance, navigation/ infotainment, self-parking, and anti-lock brakes are only possible because of semiconductor technology.

Kengeri said that Moore’s Law scaling will continue – “there’s no question about it,” he said – but there’s a growing need for new innovation to address the increasingly diverse array of semicon- ductor applications. These are driven by growth in mobile computing, development in IoT computing, the emergence of intelligent computing and augmented/virtual reality.

“Leading edge innovation will continue and all the leading manufacturers continue to invest, whether it is litho scaling in terms of EUV, or device archicture,” Kengeri said. “What is really important is how do we continue to innovate, how do we continue to get the value at competitive costs? Trying to get the scaling at any cost is not what is needed in the majority of the markets. It’s still okay at the very high end, for CPUs and servers, but in all markets, managing cost is really critical.”

“On top of all of that, we have to continue to deliver on time. Because of the complexity, things aren’t getting slower. We’re doing everything we can do continue to keep the same pace as we used to,” he added.

Kengeri said continued advances mean changing the way we think about innovation. It will require continued technical Innovation (materials and processes, device architecture and design-technology co-optimization), but – perhaps more importantly – business model innovation. This includes new thinking about long-term R&D focus/ investment, shared investments/learning/reuse, and consolidation and collaboration.