Category Archives: 3D Integration

Synopsys, Inc. (Nasdaq: SNPS) today announced the enablement of the Synopsys Design Platform and DesignWare Embedded Memory IP on GLOBALFOUNDRIES 7nm Leading-Performance (7LP) FinFET process technology. Synopsys and GF collaboration on the new process addressed several new challenges specific to the 7LP process. This process is expected to deliver 40 percent more processing power and twice the area scaling compared to GF’s 14nm FinFET process. Designers of premium mobile processors, cloud servers and networking infrastructure can take advantage of these benefits by confidently deploying the silicon-proven Synopsys Design Platform and Embedded Memory IP.

“GF’s leading-performance 7nm platform is exceeding initial performance targets and is now ready for customer designs,” said Alain Mutricy, senior vice president of product management at GF. “GF and Synopsys have collaborated to provide designers with tools and methodology that fully leverage the power and highest absolute performance of our 7LP technology, and will allow customers to create innovative products across a range of high-performance applications.”

GF and Synopsys worked together to ensure support of the comprehensive suite of Synopsys Design Platform digital implementation solutions for GF 7LP, including Design Compiler Graphical synthesis, IC Compiler II place-and-route, IC Validator physical verification, PrimeTime static timing analysis and StarRC extraction. To enable designers to achieve the full benefit of the GF 7LP process, the Synopsys tools employ advanced techniques including color track generation, pin color alignment checking and legalization, mixing of single-height and double-height physical boundary cells, power grid alignment to track and color-track aware routing.

The two companies are also collaborating on the development of Synopsys DesignWare Memory Compilers to deliver leading performance, power, area and yield for GF’s 7nm process technology. This joint effort consists of optimizing the GF 7LP process design rules and line patterns to achieve the best results. Early versions of the memory compilers will be on the GF 7LP process qualification vehicle.

“Synopsys and GF have always worked closely to address our customers’ needs, including collaborations on FDSOI and 14nm FinFET processes,” said Michael Jackson, corporate vice president of marketing and business development in the Design Group at Synopsys. “With today’s announcement, we are ready to enable designs on the 7LP process. We will continue to collaborate and ensure that our customers can get superior quality of results and faster time to results by using the Synopsys Design Platform and DesignWare Embedded Memory IP.”

The ongoing slump in shipments of standard personal computers along with the drop-off in tablets are setting the stage for cellphone IC sales to finally surpass integrated circuit revenues in total personal computing systems this year, based on new forecasts in the recently released update of IC Insights’ 2017 IC Market Drivers Report.

IC sales for cellular phone handsets are projected to grow 16% in 2017 to $84.4 billion, as shown in Figure 1, while the integrated circuit market for personal computing systems (desktop and notebook PCs, tablets, and thin-client Internet-centric units) is now forecast to increase 9% to $80.1 billion this year, according to the 150-page update to the 590-page report, originally released in 4Q16.

Fig 1

Fig 1

IC sales for both cellphones and total personal computing systems are strengthening significantly in 2017 primarily because of strong increases in the amount of money being spent on memory, with the average selling price (ASP) of DRAM expected to climb 53% and NAND flash ASP forecast to rise 28% this year. In 2016, IC sales for cellphone handsets grew 2% after rising 1% in 2015, while dollar volume for integrated circuits used in personal computing systems increased just 1% last year after falling 6% in 2015. Cellphone IC sales are also getting a lift from a projected 5% increase in shipments of smartphones, which are being packed with more low-power DRAM and nonvolatile flash storage, while growth in personal computing is expected to be held back by 3% declines in both standard personal computer and tablet unit volumes in 2017.

Shrinking shipments of desktop and notebook computers enabled cellphone IC sales to surpass integrated circuit revenues for standard PCs in 2013.  During 2015 and 2016, cellphone IC sales came close to catching up with integrated circuit sales for total personal computing systems.  In 2017, cellular phone handsets are now forecast to take over as the largest end-use systems category for IC sales.  The gap between IC sales for cellphones and total personal computing systems is projected to widen by the end of this decade.  Cellphone integrated circuit sales are expected to increase by a compound annual growth average (CAGR) of 5.3% in the 2015-2020 forecast period to $92.1 billion versus personal computing IC revenues rising by CAGR of just 2.9% to $83.8 billion in 2020, says the Update of IC Insights’ 2017 IC Market Drivers Report.

The refreshed forecast shows IC sales for standard PCs climbing 11.2% in 2017 to $67.5 billion after increasing about 4% in 2016 to $60.7 billion.  Tablet IC sales are now expected to drop 2% to $11.8 billion in 2017 after falling 11% in 2016 to $12.1 billion, based on the updated outlook.  IC sales for thin-client and Internet/cloud computing centric systems—such as laptops based on Google’s Chromebook platform design—are projected to rise 15% in 2017 to a $838 million after surging 21% in 2016 to $728 million.  Between 2015 and 2020, IC sales for standard PCs are expected to grow by a CAGR of 4.1% to $71.6 billion in the final year of the updated outlook, while table integrated circuit revenues are projected to fall by -3.9% annual rate in the period to about $11.0 billion and ICs in Internet/cloud computing are forecast to rise by CAGR of 13.8% to more than $1.1 billion.

TechInsights analysts share their view on where technology is going, how it’s changing, and what new developments are emerging.

BY STACEY WEGNER, JEONGDONG CHOE and RAY FONTAINE, TechInsights, Ottawa, ON

In 2016, wearables were extremely interesting mainly because there was so much uncertainty around whether or not the market will be viable. The year saw some truly low-cost smart and fitness devices, and some market surprises like Fitbit buying Pebble. The Apple Watch 2 was an improvement over the Watch 1. However, the Huawei watch is remarkably designed with a nice round face, and functional, making the decision on which smart- watch to buy difficult.

While wearables will remain intriguing, even more interesting to watch is the wearables market. Hearables can be as simple as ear buds and basic hearing aids or as complex as devices that correct and amplify sound, sync with wireless devices for virtually any application, and even measure biometric outputs. That’s just the beginning. New sensors being packed into small devices are bringing us devices with nearly 30 sensors per device.

Our recent AirPod teardown (FIGURES 1 and 2) sheds even more light on what’s happening in this area. The W1 chip found in the Beats Studio wireless headphone has the package mark 343S00131. Meanwhile, the W1 chip torn down from the Apple AirPods has the package mark 343S00130. They have a slight difference in the last digit in the package marks. TechInsights has confirmed that both 343S00131 and 343S00130 have the same die. This die measures 4.42 mm x 3.23 mm = 14.3 mm2 . TechInsights has been tracking Internet of Things (IoT) SoCs for over a year and our observations indicate that this new W1 SoC is very competitively placed when comparing its die size and connectivity specification of Bluetooth 4.2 or greater.

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Another extremely interesting technology to watch is the rise of intelligent personal or family assistants. This market started with the introduction of the popular Alexa and Echo. Sony may release their assistant this year with more sure to follow. As far as timing, we will have to wait and see. One issue that needs to be addressed is data collection and usage vs. persona privacy in a manner similar to Vizio’s issues with the FTC. In addition, more changes are coming for artificial intelligence or assistants on mobile devices with Samsung announcing Bixby ahead of its G8 launch.
Of course there are a slew of IoT technologies to watch like the acceptance of Zigbee, Z-Wave, LoRa, and Bluetooth 5.0, all of which seem to be vying aggressively for consumer IoT/connected home market. Rumors are gaining strength around how the Samsung S8 will have Bluetooth 5, which could mean a new WiFi modem, from whom we are not certain. Samsung and Wisol have been aligned for a while, but it would be a big statement to see a Samsung/Wisol WiFi/ Bluetooth modem design supporting a new technology like Bluetooth 5.0 in a flagship phone. Based on our knowledge of the Bluetooth Special Interest Group, we don’t believe that Bluetooth 5.0 has to be declared for a product. If fact, it would almost seem as if the SiG is asking OEMs to not make a declaration of the Bluetooth 5 in the device.

Image sensors

2016 was an exciting year for smartphone cameras, which should be considered as one of the biggest hardware differentiators between mobile handset platforms. Dual camera systems have reached the mainstream and are forecasted to drive growth for CMOS image sensor IDMs and foundries. Samsung introduced full chip Dual Pixels implemented in chips from its team and from Sony. Each Dual Pixel photosite is available as an autofocus (AF) point, and this complements traditional contrast AF methods and the emerging laser + time-of-flight (ToF) systems.

In 2017, ToF is expected to be a key differentiator in mobile platforms, both for AF and for new 3D/ranging functionality. Sony has introduced first generation direct bond interconnect (DBI) as a through silicon via (TSV) replacement and we expect tighter pitch DBI and eventually full chip active DBI going forward. On the image signal processor (ISP) side we are seeing a big push to lower nodes (28 nm ISPs are the state-of-the-art for high end stacked CIS chips). The flexibility offered by chip stacking should lead to new and disruptive partnerships between CMOS image sensor specialists and mixed signal advanced CMOS specialists. Finally, we expect new entrants to the digital imaging and sensing landscape. Machine vision, robotics, ranging, surveillance/security, and automotive vision and sensing applications are all positioned for growth due to enabling functionality and continued performance gains. It’s certainly an exciting time for all involved in designing and fabricating imaging and sensing pixel arrays and camera systems!

Memory devices

Last year virtually every vendor, device manufacturers, R&D engineer and market analyst we talked to was focused on DRAM and NAND technology roadmaps. We still talk to clients today who are focused on the future of these technologies. Today, 32L and 48L 3D NAND products are common and all the NAND players are eager to develop the next generation 3D NAND products such as 64L and 128L or even more (FIGURE 3). TechInsights has been analyzing and comparing these devices regularly. We found that 3D NAND is a kind of revolution for memory devices, and because of it, big data or data center, SSD/SD and related technologies like controller, interface and board/package, are moving forward. In addition, they may be able to keep pace for more than the next five years until any new emerging memory devices are commercialized.

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The memory products/technologies we are anticipating this year are 3D NAND technology with 64L, 72L and 128L and 1x and 1y nm DRAM technology. As always, 3D NAND technology is competitive with emerging memory including X-point memory regarding on the performance, reliability, retention, process integration and cost since X-point memory and crossbar devices such as ReRAM, CBRAM, MRAM and PCRAM are likely not cost effective (bit cost).

While Samsung has already revealed 1x nm DRAM, in 2017, we believe there will be another big area of competition in DRAM technology (FIGURE 4). DRAM cell has 1T1C architecture with a cylindrical capacitor, however, nowadays, the cell capacitance cannot meet the capacitance spec (20fF/ cell). Commercial DRAM products such as Samsung’s 18nm DRAM have just about 12fF/cell. With smaller cell nodes, it is absolutely harder to get the sufficient cell capacitance. Nevertheless, Samsung and SK-hynix are confident in developing n+1 (1y nm) and n+2 (1z nm). We anticipate that in 2017, every DRAM maker will be developing 1x and 1y nm commercial DRAM products. How these rollout and perform remains to be seen.

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Finally, we are anticipating a commercial product using X-point memory from Micron and Intel.

Conclusion

These represent some of the major technologies we have our eye on this year, although we fully anticipate seeing new technologies we can only imagine today emerge. After all, change is truly the only constant in our world. As our analysts continue to examine and reveal the innovations other can’t inside advanced technology, we will continue to share our findings on the technologies noted above, how they are used, and how they will be changed by the next discovery or invention.

BY DR. PHIL GARROU, Contributing Editor

The need for ever more computational power continues to grow and exaflop (1018 ) capabilities may soon become necessary. A paper by AMD on “Design and Analysis of an APU for Exascale Computing” presented at the IEEE High Performance Computing Architec- tures Conference (HPCA) gave the AMD vision for an exascale node architecture for exascale computing including low-power and high-performance CPU cores, integrated energy-efficient GPU units, in-package high-bandwidth 3D memory, die-stacking and chiplet technologies, and advanced memory systems.

Two of the building blocks for this exascale node architecture are (1) it’s chiplet-based approach that decouples performance-critical processing components like CPUs and GPUs from components that do not scale well with technology (e.g., analog components), allowing fabrication in individually optimized process technologies for cost reduction and design reuse in other market segments and (2) the use of in-package 3D memory, which is stacked directly above high- bandwidth-consuming GPUs.

The exascale heterogeneous processor (Figure 1) is an accelerated processing unit (APU) consisting of CPU and GPU compute integrated with in-package 3D DRAM. The overall structure makes use of a modular “chiplet” design, with the chiplets 3D-stacked on other “active interposer” chips. “The use of advanced packaging technologies enables a large amount of computational and memory resources to be located in a single package.” The exascale targets for memory bandwidth and energy efficiency are incredibly challenging for off-package memory solutions. Thus AMD proposes to integrate 3D-stacked DRAM into the EHP package.

In the center of the EHP are two CPU clusters, each consisting of four multi-core CPU chiplets stacked on an active interposer base die. On either side of the CPU clusters are a total of four GPU clusters, each consisting of two GPU chiplets on a respective active interposer. Upon each GPU chiplet is a 3D stack of DRAM. The DRAM is directly stacked on the GPU chiplets to maximize bandwidth. The interposers underneath the chiplets provide interconnection between the chiplets along with other functions such as external I/O interfaces, power distribution and system management. Interposers maintain high-bandwidth connectivity among themselves by utilizing wide, short distance, point-to-point paths.

Chiplets

The performance requirements require a large amount of compute and memory to be integrated into a single package. Rather than build a single, monolithic system on chip (SOC), AMD proposes to leverage advanced die-stacking technologies to decompose the EHP into smaller components consisting of active interposers and chiplets. Each chiplet houses either multiple GPU compute units or CPU cores. The chiplet approach differs from conventional multi-chip module (MCM) designs in that each individual chiplet is not a complete chip. For example, the CPU chiplet contains CPU cores and caches, but lacks memory interfaces and external I/O.

A monolithic SOC imposes a single process technology choice on all components in the system. With chiplets and interposers, each discrete piece of silicon can be optimized for its own functions. It is expected that smaller chiplets will have higher yield due to their size, and when combined with KGD testing, can be assembled into larger systems at reasonable cost.

It is expected that the decomposition (or disintegration as I prefer to call it) of the EHP into smaller pieces will enable silicon-level reuse of IP (note – this is one of the main drivers of the DARPA CHIPS program)

Yole Développement (Yole) confirms the consolidation of the advanced packaging industry, that is showing a steady growth between 2016 and 2022: +7% in revenue.

“Advanced packaging is showing a total revenue CAGR higher than the total packaging industry (3-4%), semiconductor industry (4-5%) and generally the global electronics industry (3-4%)”, comments Andrej Ivankovic, Technology & Market Analyst at Yole. “Companies are today managing production costs and enlarging their portfolio. In parallel, advanced packaging players are expanding their activities toward the emerging markets thanks to mergers & acquisitions,” he adds. Therefore, the advanced packaging industry is showing drivers including IoT, automotive industry, 5G connectivity, AR/VR, AI.

advanced packaging revenue

What are the advanced packaging market drivers and latest market dynamics? What are the emerging market segments targeted by the leaders to diversify their activities? What are the technology moves? How will the advanced packaging market affect the semiconductor industry evolution? Advanced packaging solutions could enable the development of future semiconductor products and so boost the global semiconductor industry.

Yole’s advanced packaging team releases this month its Status of the Advanced Packaging Industry report. Under this 2017 edition, analysts propose an overview the industry, its disruptions and opportunities. They analyze the latest technology trends and forecasts. Yole’s team also reviews the supply chain and offers a detailed description and analysis of leading company strategies, especially the shifting business models. Yole’s report includes a technical roadmap, showing an analysis per advanced packaging platform along with an analysis of future production and developments in the timeframe 2017-2022.

Andrej Ivankovic from Yole, author of this technology & market report, will present a closer look at the ASE Tech Forum @ Nijmegen. ASE’s conference takes place on June 28, in Van der Valk Hotel, Nijmegen, The Netherlands. During one day, ASE invites you to explore key areas of its IC , SiP and MEMS packaging portfolio, developed in alignment with emerging applications. Innovative technologies, such as FO , FC and 3D, will be detailed as well as opportunities of collaboration: Full program & registration.

“We are very pleased to welcome our network at the ASE Tech Forum @ Nijmegen on June 28”, asserts Jean-Marc Yannou, Technical Director at ASE Europe. ASE is developing a unique one-day program to present our innovative portfolio and including networking times and technology demonstrations. We are looking forward to welcome the advanced packaging companies and get relevant discussions and debates”.

“The fastest growing advanced packaging platform is FO with 36% followed by 2.5D/3D TSV with 28%”,announces Andrej Ivankovic from Yole. “Therefore FO platforms and 2.5D/3D TSV solutions are expected to exceed respectively US$3 billion and US$ 1.3 billion by 2022.”

The FC platform is by far the largest, accounting for 81% of advanced packaging revenue with US$19.6 billion in 2017, however a lower 5% revenue growth indicates that penetration of primarily FO packages will decrease FC market share to 74% by 2022. The revenue forecast translates to an advanced packaging wafer forecast of 8% and a 9% unit count, CAGR during the period 2016-2022. Advanced packages will continue to dominantly address high-end logic and memory in computing and telecom, with further penetration in analog and RF in high-end consumer/mobile segments, while eyeing opportunities in growing automotive and industrial segments.

The shifts in the semiconductor supply chain are results of preparations for future uncertainty, and search for other value flows. Several mergers and acquisitions have been made in attempt to offer a more complete and diversified portfolio, while keeping control of costs and potential losses. Furthermore, in search of additional revenue, new business models are appearing or expanding.

GLOBALFOUNDRIES this week announced the availability of its 7nm Leading-Performance (7LP) FinFET semiconductor technology, delivering a 40 percent generational performance boost to meet the needs of applications such as premium mobile processors, cloud servers and networking infrastructure. Design kits are available now, and the first customer products based on 7LP are expected to launch in the first half of 2018, with volume production ramping in the second half of 2018.

In September 2016, GF announced plans to develop its own 7nm FinFET technology leveraging the company’s unmatched heritage of manufacturing high-performance chips. Thanks to additional improvements at both the transistor and process levels, the 7LP technology is exceeding initial performance targets and expected to deliver greater than 40 percent more processing power and twice the area scaling than the previous 14nm FinFET technology. The technology is now ready for customer designs at the company’s leading-edge Fab 8 facility in Saratoga County, N.Y.

“Our 7nm FinFET technology development is on track and we are seeing strong customer traction, with multiple product tapeouts planned in 2018,” said Gregg Bartlett, senior vice president of the CMOS Business Unit at GF. “And, while driving to commercialize 7nm, we are actively developing next-generation technologies at 5nm and beyond to ensure our customers have access to a world-class roadmap at the leading edge.”

GF also continues to invest in research and development for next-generation technology nodes. In close collaboration with its partners IBM and Samsung, the company announced a 7nm test chip in 2015, followed by the recent announcement of the industry’s first demonstration of a functioning 5nm chip using silicon nanosheet transistors. GF is exploring a range of new transistor architectures to enable its customers to deliver the next era of connected intelligence.

GF’s 7nm FinFET technology leverages the company’s volume manufacturing experience with its 14nm FinFET technology, which began production in early 2016 at Fab 8. Since then, the company has delivered “first-time-right” designs for a broad range of customers.

To accelerate the 7LP production ramp, GF is investing in new process equipment capabilities, including the addition of the first two EUV lithography tools in the second half of this year. The initial production ramp of 7LP will be based on an optical lithography approach, with migration to EUV lithography when the technology is ready for volume manufacturing.

AI is driving the development of 3D TSV and heterogeneous integration technologies. With its new 3D TSV & 2.5D business update report, Yole Développement (Yole), part of Yole Group of Companies investigates the advanced packaging industry and takes a closer look on the AI impact on this market.

“3D integration is clearly offering today unequalled performances suiting exactly the pressing needs of AI applications,” commented Emilie Jolivet, Technology & Market Analyst at Yole.

Initially developed for niche markets including MEMS devices and memories for datacenters, 3D integration is entering in a new era. The world population increase, the exploding smartphones market, the development of new functionalities such as voice/image recognition… all these parameters directly contribute to the development of AI and deep learning solutions, all based on 3D integration technologies. AI is not a concept anymore but a reality that is skyrocketing the development of disruptive advanced packaging technologies.

This year, the “More than Moore” market research and strategy consulting company is moving a step forwards the applications side. Its advanced packaging & semiconductor manufacturing team investigates the industry evolution, taking into account promising sectors such as deep learning, the end-users’ needs and required specifications for final systems. Yole’s analysts combine their advanced packaging expertise and their knowledge of the different industries to perform up-to-date and innovative reports. The 3D TSV & 2.5D business update report is a good example, with a strong focus on the high-performance sector.

Why do we need 3D TSV solutions, especially in high performance applications?

According to Yole, benefits are numerous and are part of the major issues initially identified by the industrial companies. Bandwidth, latency and power consumption are the key words of these innovations… Emilie Jolivet from Yole details some below:

  •  When two chips or more are integrated on an interposer, distance between logic and memory is shortened which enables lower latency and lower power consumption.
•  DRAM, based on a 3D TSV solution, is offering an unequalled bandwidth performance because of the ability of TSV solution to connect several layers of the device.
•  Artificial intelligence and specifically deep learning mostly intensively using memory and computing also need 3D TSV approaches. Both applications are driving the demand of interposer and 3D memory cubes.

AI and deep learning, both part of the high performance applications segment are might be the most impressive applications. However, datacenter networking, AR/VR and autonomous driving are not so far behind. Industrial companies progressively penetrate these market segments by developing dedicated approaches:

  •  Both 3D IC leaders, TSMC and Globalfoundries are involved in the development of new solutions focused on 3D SoC.
•  Samsung introduced its interposer solutions in 2017, SPIL is developing its own 2.5D solutions
•  STMicroelectronics is working on 3D interconnections and interposers for various applications including silicon photonics, data centers.

In addition, companies like Intel, Nvidia are completely re-thinking their growth strategy: “Major IC companies which missed the smartphone business clearly don’t want to miss the AI revolution,” commented Emilie Jolivet from Yole. From their side, investors are part of the playground. Therefore, they all re-align their strategy to have product portfolio for serving AI/deep learning needs. Datacenters, cloud computing, AI, autonomous driving are becoming key words for venture capitalists.

Yole’s analysts are convinced of the added value of 3D integration technologies. AI and deep learning are new applications to consider but not only. AR/VR will be also part of the 3D integration future. And the latest announcement from AMD regarding its new Radeon Pro Vega graphic card dedicated to Apple’s new iMac Pro is another step towards the computing applications™.

A detailed description of the 3D TSV and 2.5D Business Update – Market and Technology Trends 2017 is available on i-micronews.com, advanced packaging reports section.

Imec, a research and innovation hub in nanoelectronics and digital technology, announced today at the 2017 Symposia on VLSI Technology and Circuits the world’s first demonstration of a vertically stacked ferroelectric Al doped HfO2 device for NAND applications. Using a new material and a novel architecture, imec has created a non-volatile memory concept with attractive characteristics for power consumption, switching speed, scalability and retention. The achievement shows that ferro-electric memory is a highly promising technology at various points in the memory hierarchy, and as a new technology for storage class memory. Imec will further develop the concept in collaboration with the world’s leading producers of memory ICs.

Ferro-electric materials consist of crystals that exhibit spontaneous polarization; they can be in one of two states, which can be reversed with a suitable electric field. This non-volatile characteristic resembles ferromagnetism, after which they have been named. Discovered more than five decades ago, ferro-electric memory has always been considered ideal, due to its very low power needs, non-volatile character and high switching speed. However, issues with the complex materials, the breakdown of the interfacial layer and bad retention characteristics have presented significant challenges. The recent discovery of a ferro-electric phase in HfO2, a well-known and less complex material, has triggered a renewed interest in this memory concept.

“With HfO2, there is now a material with which we can process ferro-electric memories that are fully CMOS compatible. This allows us to make a ferro-electric FET (FeFET) in both planar and vertical varieties,” noted Jan Van Houdt, imec’s chief scientist for memory technology. “We are working to overcome some of the remaining issues, such as retention, precise doping techniques and interface properties, in order to stabilize the ferro-electric phase. We are now confident that our FeFET concept has all the required characteristics. It is, in fact, suitable for both stand-alone and embedded memories at various points in the memory hierarchy, going all the way from non-volatile DRAM to Flash-like memories. It has particularly interesting characteristics for future storage-class memory, which will help overcome the current bottleneck caused by the differences in speed between fast processors and slower mass memory.”

Imec recently presented the first, extremely positive results to its partners. The research center is now offering further development and industrialization of the vertical FeFET as a program to all its memory partners, which include the world’s major companies producing memory ICs.

“FeFETs can be used as a technology to build memory very similar to Flash-memory, but with additional advantages for further scaling, simplified processing, and power consumption,” added Van Houdt. “With our longstanding R&D and processing experience on advanced Flash, we are uniquely positioned to offer our partners a head start in this exciting opportunity. They can then decide how best to fit ferro-electric memories in their products and chips.”

Imec’s research into advanced memory is performed in cooperation with imec’s key partners in its core CMOS programs including GlobalFoundries, Intel, Micron, Qualcomm, Samsung, SK Hynix, Sony Semiconductor Solutions, Toshiba, Sandisk and TSMC.

imec ferroelectric

The Semiconductor Industry Association (SIA) today welcomed a new $75 million initiative outlined in the President’s fiscal year 2018 budget proposal and funded through the Defense Advanced Research Projects Agency (DARPA) that would bolster long-term semiconductor research. The public-private “electronics resurgence” initiative would advance research to progress beyond the limits of traditional scaling and catalyze next-generation semiconductor materials, designs, and architectures. The program would combine with DARPA’s other microelectronics R&D initiatives for a total of more than $200 million devoted to semiconductor and related technology research in the coming fiscal year, an amount that will be supplemented by significant industry investments.

“Semiconductors, the brains of modern electronics, are fundamental to America’s economic, technological, and military infrastructure,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Advances in semiconductor technology reverberate throughout society, making technology more affordable and accessible to consumers and boosting U.S. innovation, productivity, and economic growth. DARPA’s new initiative would strengthen long-range semiconductor research, enhance semiconductor technology’s positive impacts on our country, and bolster national security. The semiconductor industry has a long record of partnering with our government to advance early-stage research. This new, forward-looking program is yet another important example of this ongoing collaboration, and we are committed to working with the Administration and Congress to ensure its enactment.”

The new DARPA initiative is expected to focus on the development of new materials for use in electronics devices, nontraditional architectural approaches, and innovative circuit designs, among other research areas. In addition to fostering advancements in semiconductor technologies used for national security, the ripple effect from this research will be felt across the full range of semiconductor applications: communications, computing, health care, transportation, clean energy, and countless others.

As one of America’s top exporters and advanced manufacturers, the U.S. semiconductor industry is a key contributor to our country’s strength. Our industry supports more than one million jobs in America, accounts for nearly half of the world’s chip sales, and is the world’s most innovative sector. And the United States is home to almost half of U.S. semiconductor companies’ manufacturing base, across 21 states.

“Our industry’s continued strength, and the myriad benefits it provides to our country, are directly attributable to large and sustained investments in research,” said Neuffer. “Recognizing this, the U.S. semiconductor industry plows about one-fifth of its annual sales back into research and development, among the most of any industry. The new DARPA initiative marks a major commitment to furthering semiconductor technology and keeping America at the head of the class in innovation.”

Neuffer also noted SIA’s longstanding support for basic scientific research funded through other federal agencies such as the National Science Foundation (NSF), the National Institute of Standards and Technology (NIST), and the Department of Energy (DOE) Office of Science. He expressed the semiconductor industry’s eagerness to work with the Administration and Congress to enact a budget that prioritizes the strategic importance of research investments to America’s economic and national security and technological leadership.

 

Mentor, a Siemens business, today announced that it has launched the Mentor OSAT (outsourced assembly and test) Alliance program to help drive ecosystem capabilities in support of new high-density advanced packaging (HDAP) technologies like 2.5D IC, 3D IC and fan-out wafer-level packaging (FOWLP) for customer integrated circuit (IC) designs. By launching this program, Mentor will work with OSATs to provide fabless companies with design kits, certified tools, and best practices to aid in smoother adoption of these new packaging solutions that require a much tighter link between chip and package design. Mentor also announced Amkor Technology, Inc. as its first OSAT Alliance member.

Through the Mentor OSAT Alliance, members work with Mentor to create certified design kits to help customers speed up IC and advanced package development with Mentor’s Tanner L-Edit AMS design cockpit, Calibre IC physical verification platform, HyperLynx SI/PI and HyperLynx full-wave 3D tools, Xpedition Substrate Integrator and Xpedition Package Designer tools, and Mentor’s newly announced Xpedition HDAP flow.

“Mentor’s customers are pioneering technologies at the heart of IoT, autonomous driving and next-generation wired and wireless networks,” said Joe Sawicki, vice president and general manager of the Design to Silicon Division at Mentor. “Many of these companies are designing ICs that use advanced packaging from OSATs to achieve their design goals. Like the Mentor Foundry Alliance program did for accelerating foundry design kit creation, the Mentor OSAT Alliance program will help our mutual customers use Mentor’s world-class EDA portfolio to more easily implement ICs with advanced packaging technologies.”

Members of the Mentor OSAT Alliance will receive software, training, and reference flow best practices from Mentor, in addition to the opportunity for co-marketing mutual offerings.

“The next generation of IC packaging will require increased heterogeneous die integration, incorporating reduced size, weight, and improved performance and reliability,” said Ron Huemoeller, corporate vice president, research and development at Amkor. “Amkor’s Silicon Wafer Integrated Fan-out Technology (SWIFT™) package technology is designed to provide increased I/O and circuit density within a significantly reduced footprint and profile for single and multi-die applications. Being an integral part of the Mentor OSAT Alliance program will allow us to fast-track PDK development and delivery, and enable our customers to design more efficiently and predictably.”

With alliance programs for both foundries and OSATs, Mentor continues to enable the semiconductor ecosystem. The OSAT Alliance program will drive global design and supply chain adoption of these emerging advanced packaging technologies.