Category Archives: 3D Integration

An engineer with the Erik Jonsson School of Engineering and Computer Science at The University of Texas at Dallas has designed a novel computing system made solely from carbon that might one day replace the silicon transistors that power today’s electronic devices.

“The concept brings together an assortment of existing nanoscale technologies and combines them in a new way,” said Dr. Joseph S. Friedman, assistant professor of electrical and computer engineering at UT Dallas who conducted much of the research while he was a doctoral student at Northwestern University.

The resulting all-carbon spin logic proposal, published by lead author Friedman and several collaborators in the June 5 issue of the online journal Nature Communications, is a computing system that Friedman believes could be made smaller than silicon transistors, with increased performance.

Today’s electronic devices are powered by transistors, which are tiny silicon structures that rely on negatively charged electrons moving through the silicon, forming an electric current. Transistors behave like switches, turning current on and off.

In addition to carrying a charge, electrons have another property called spin, which relates to their magnetic properties. In recent years, engineers have been investigating ways to exploit the spin characteristics of electrons to create a new class of transistors and devices called “spintronics.”

Friedman’s all-carbon, spintronic switch functions as a logic gate that relies on a basic tenet of electromagnetics: As an electric current moves through a wire, it creates a magnetic field that wraps around the wire. In addition, a magnetic field near a two-dimensional ribbon of carbon — called a graphene nanoribbon — affects the current flowing through the ribbon. In traditional, silicon-based computers, transistors cannot exploit this phenomenon. Instead, they are connected to one another by wires. The output from one transistor is connected by a wire to the input for the next transistor, and so on in a cascading fashion.

In Friedman’s spintronic circuit design, electrons moving through carbon nanotubes — essentially tiny wires composed of carbon — create a magnetic field that affects the flow of current in a nearby graphene nanoribbon, providing cascaded logic gates that are not physically connected.

Because the communication between each of the graphene nanoribbons takes place via an electromagnetic wave, instead of the physical movement of electrons, Friedman expects that communication will be much faster, with the potential for terahertz clock speeds. In addition, these carbon materials can be made smaller than silicon-based transistors, which are nearing their size limit due to silicon’s limited material properties.

“This was a great interdisciplinary collaborative team effort,” Friedman said, “combining my circuit proposal with physics analysis by Jean-Pierre Leburton and Anuj Girdhar at the University of Illinois at Urbana-Champaign; technology guidance from Ryan Gelfand at the University of Central Florida; and systems insight from Alan Sahakian, Allen Taflove, Bruce Wessels, Hooman Mohseni and Gokhan Memik at Northwestern.”

While the concept is still on the drawing board, Friedman said work toward a prototype of the all-carbon, cascaded spintronic computing system will continue in the interdisciplinary NanoSpinCompute research laboratory, which he directs at UT Dallas.

Silicon based CMOS (Complementary metal-oxide semiconductors) technology has truly shaped our world. It enables most of the electronics that we rely on today including computers, smartphones and digital cameras. However, to continue the path of progress in the electronics industry new technology must be developed and a key feature of this is the ability to integrate CMOS with other semiconductors. Now, Graphene Flagship researchers from ICFO (The Institute of Photonic Sciences in Barcelona) have shown that it is possible to integrate graphene into a CMOS integrated circuit.

This is graphene integrated onto CMOS pixels. Credit: Fabien Vialla

This is graphene integrated onto CMOS pixels. Credit: Fabien Vialla

In their paper published in the journal Nature Photonics they combine this graphene-CMOS device with quantum dots to create an array of photodetectors, producing a high resolution image sensor. When used as a digital camera this device is able to sense UV, visible and infrared light at the same time. This is just one example of how this device might be used, others include in microelectronics, sensor arrays and low-power photonics.

“The development of this monolithic CMOS-based image sensor represents a milestone for low-cost, high-resolution broadband and hyperspectral imaging systems” ICREA Professor at ICFO, Frank Koppens, highlights. He assures that “in general, graphene-CMOS technology will enable a vast amount of applications, that range from safety, security, low cost pocket and smartphone cameras, fire control systems, passive night vision and night surveillance cameras, automotive sensor systems, medical imaging applications, food and pharmaceutical inspection to environmental monitoring, to name a few”.

These results were enabled by the collaboration between Graphene Flagship Partner Graphenea (a Spanish graphene supplier) and ICFO, within the optoelectronics workpackage of the Graphene Flagship.

By creating a hybrid graphene and quantum dot system on a CMOS wafer using a layering and patterning approach, the Flagship team solved a complex problem with a simple solution. First the graphene is deposited, then patterned to define the pixel shape and finally a layer of PbS colloidal quantum dots is added. The photoresponse of this system is based on a photogating effect, which starts as the quantum dot layer absorbs light and transfers it as photo-generated holes or electrons to the graphene, where they circulate due to a bias voltage applied between two pixel contacts. The photo signal is then sensed by the change in conductivity of the graphene, with graphene’s high charge mobility allowing for the high sensitivity of the device.

As Stijn Goossens comments, “No complex material processing or growth processes were required to achieve this graphene-quantum dot CMOS image sensor. It proved easy and cheap to fabricate at room temperature and under ambient conditions, which signifies a considerable decrease in production costs. Even more, because of its properties, it can be easily integrated on flexible substrates as well as CMOS-type integrated circuits.”

The commercial applications of this research and the potential for imaging and sensing technology are now being explored in ICFO’s Launchpad incubator.

Professor Andrea Ferrari, Science and Technology Officer and Chair of the Management Panel of the Graphene Flagship added: “The integration of graphene with CMOS technology is a cornerstone for the future implementation of graphene in consumer electronics. This work is a key first step, clearly demonstrating the feasibility of this approach. The Flagship has put a significant investment in the system level integration of graphene, and this will increase as we move along the technology and innovation roadmap”.

IC Insights recently released its May Update to the 2017 McClean Report. This Update included IC Insights’ latest 2017 IC market forecast, a discussion of the 1Q17 semiconductor industry market results, a review of the IC market by electronic system type, a look at the top-25 1Q17 semiconductor suppliers, and an update of the capital spending forecast by company.

Figure 1 shows the “Billion-Dollar Club” list from 2007 through IC Insights’ forecast in 2017. In total, there are 15 companies that are forecast to have semiconductor capital expenditures of ≥$1.0 billion in 2017, up from 11 in 2016 and only 8 in 2013. Infineon and Renesas are expected to move into the major spending ranking this year as each company is aggressively targeting the fast rising automotive semiconductor market. Other companies expected to be added to the ranking this year include Nanya and ST. Moreover, IC Insights believes that a few Chinese companies are likely to break into the “major spenders” ranking over the next couple of years as they ramp up their new fabs. The 15 companies listed, which include four pure-play foundries, are forecast to represent 83% of total worldwide semiconductor industry capital spending in 2017, the highest percentage over the timeperiod shown.

This year, four companies—Intel, Samsung, GlobalFoundries, and SK Hynix— are expected to represent the bulk of the increase in spending. Samsung is forecast to spend $3,200 million more in capital outlays this year than in 2016, Intel $2,375 million more, GlobalFoundries $865 million more, and SK Hynix an additional $812 million. Combined, these four companies are expected to increase their spending by $7,252 million in 2017, or about 90% of the total $8,021 million net jump in total semiconductor industry capital expenditures forecast for this year.

With a 31% increase, the DRAM/SRAM segment is expected to display the largest percentage increase in capital expenditures of the major products types listed this year. With DRAM ASPs surging since the third quarter of 2016, DRAM manufacturers are once again stepping up spending for this segment.

Capital spending for flash memory in 2016 ($14.6 billion) was significantly higher than spending allocated for DRAM ($8.5 billion). Overall, IC Insights believes that essentially all of the spending for flash memory in 2016 and 2017 was and will be dedicated to 3D NAND flash memory process technology as opposed to planar flash memory. A big jump in NAND flash capital spending in 2017 is expected to come from Samsung as it ramps its 3D NAND production in its giant new fab in Pyeongtaek, South Korea.

Figure 1

Figure 1

By Walt Custer, Custer Consulting Group, and Dan Tracy, SEMI

SEMI’s year-to-date worldwide semiconductor equipment billings year-to-date through March show a 59.6 percent gain to the same period last year.

Understanding volatility in the electronic equipment supply chain can be valuable in forecasting future business activity.  A useful way to compare relevant electronic industry data series is by using 3/12 growth rates.  The 3/12 growth is the ratio of three months of data, compared to the same three months a year earlier.

Chart 1 compares the 3/12 growth rates of four data series:

  • World semiconductor equipment shipments (SEMI; www.semi.org)
  • Taiwan chip foundry sales (company composite maintained by Custer Consulting Group)
  • World semiconductor shipments (SIA, www.semiconductors.org & WSTS, www.wsts.org)
  • World electronic equipment sales (composite of 238 global OEMS maintained by Custer Consulting Group).

supply-chain-dynamics

Highlights

  • Semiconductor capital equipment sales are by far the most volatile of the four series in Chart 1, followed by foundry sales.
  • Foundry sales are a good leading indicator for semiconductor equipment shipments ─ leading SEMI equipment by 3-4 months on a 3/12 growth basis.
  • Foundry growth peaked in November 2016.
  • SEMI equipment growth appears to have peaked in February 2017.
  • Semiconductor shipments may have peaked in March 2017. March semiconductor revenues were up 18.5 percent in 1Q’17 vs 1Q’16 and, although still very strong, their rate of growth appears to have plateaued.

Note that 3/12 values greater than 1.0 indicate growth.  Declining 3/12 values (but greater than 1.0) indicate growth but at a slower rate.  Values below 1.0 indicate contraction.

Based upon Chart 1, semiconductor equipment 3/12 growth will likely reach zero in August or September of this year. Considering the unstable world geopolitical situation, uncertainty clearly exists.

SEMI members can access member-only market data and information at www.semi.org/en/free-market-data-semi-members.

Custer Consulting Group (www.custerconsulting.com) provides market research, business analyses and forecasts for the electronic equipment and solar/photovoltaic supply chains including semiconductors, printed circuit boards & other passive components, photovoltaic cells & modules, EMS, ODM & related assembly activities and materials & process equipment.

Imec, a research and innovation hub in nano-electronics and digital technologies, and Cascade Microtech, a FormFactor company, announced the successful development of a fully-automatic system for pre-bond testing of advanced 3D chips. Pre-bond testing is important to increase the yield of 3D stacked chips. The new system enables probing and hence testing of chips with large arrays of 40µm-pitch micro-bumps, on 300mm wafers. The relevance of this new tool is underlined by winning the 2017 National Instruments Engineering Impact Award yesterday at a ceremony in Austin, Texas.

As an emerging technology, 3D IC stacking still has many open options and technical challenges. One of these challenges is probing of the individual chips, before being stacked, to ensure a good yield of the 3D stacked ICs. The inter-chip connections of 3D stacked ICs are made by large arrays of fine-pitch micro-bumps which makes probing these bumps a challenge. Until today, the probing solution is to add dedicated pre-bond probe pads to the to-be-stacked dies, but this requires extra space and design effort and increases test time.

Imec and Cascade Microtech have now developed a fully automatic test cell that can provide test access by probing large arrays of fine-pitch micro-bumps. The system is based on a Cascade Microtech CM300 probe station and National Instruments PXI test instrumentation, complemented by in-house developed software for automatic test generation, data analysis, and visualization. The system allows testing of wafers up to 300mm diameter, including thinned wafers on tape frame with exposed through-silicon vias. After several years of intense collaboration between imec and Cascade Microtech, partly supported by the EU-funded FP7 SEA4KET project, good results were achieved with Cascade Microtech’s Pyramid Probe prototype RBI probe cards on imec’s 300mm wafers with 40µm-pitch micro-bumped chips.

“Imec provided us with unique early insights into the test requirements for 3D ICs, which drove the development of this system,” said Jörg Kiesewetter, director of engineering at Cascade Microtech Dresden. “Also the availability of imec’s dedicated micro-bump test wafers has helped us to fine-tune both the probe station and the probe cards for this application.”

“At imec, we are using the system now on a routine basis to test our 40µm-pitch micro-bumped wafers,” stated Erik Jan Marinissen, principal scientist at imec. “As everything in the semiconductor realm, also micro-bumps are subject to downscaling. Hence, with Cascade, we have started experiments to also probe our 20µm-pitch micro-bump arrays, and those look promising.”

Electronic systems that improve vehicle performance; that add comfort and convenience; and that warn, detect, and take corrective measures to keep drivers safe and alert are being added to new cars each year. Consumer demand and government mandates for many of these new systems, along with rising prices for many IC components within them, are expected to raise the automotive IC market 22% this year to a new record high of $28.0 billion (Figure 1).

Over the past several years, the global automotive IC market has experienced some extraordinary swings in growth.  After increasing 11.5% in 2014, the automotive IC market declined 2.5% in 2015, but then rebounded with solid 10.8% growth in 2016.  It is worth noting that the sales decline experienced in 2015 was primarily the result of falling ASPs across all the key automotive IC product categories—microcontrollers, analog ICs, DRAM, flash, and general- and special-purpose logic ICs, which offset steady unit growth for automotive ICs that year.

Figure 1

Figure 1

However, in the second half of 2016, steadily rising ASPs (along with demand for the new automotive systems) helped return the automotive IC market to double-digit growth. In 2017, exceptionally strongincreases in DRAM and flash memory prices are expected to help drive the total automotive IC market to an extraordinary increase of 22.4%.

IC Insights recently revised its IC market outlook for 2017 and now shows DRAM average selling prices rising 50% in 2017, NAND flash ASPs increasing 28%, and the average selling price for automotive special-purpose logic devices increasing 34%. these strong ASPs gains, coupled with ongoing system demand, are driving the strong automotive IC market growth this year (Figure 2).

Figure 2

Figure 2

Collectively, microcontrollers, analog, standard logic, and memory ICs used in automotive applications accounted for only about 8% of total IC marketshare by system type in 2016, but that share is forecast to increase to more than 10% in 2020, when automotive is expected to become the third-largest end-use category for ICs, trailing only the communications and computer segments.   Through 2020, IC Insights anticipates that advanced driver-assistance systems (ADAS) will be the biggest user of automotive ICs.  Various ADAS systems are currently helping cars and drivers remain safe on the road and they are proving to be essential building blocks to semi autonomous and autonomous vehicles that are being proposed for the next decade.

Synopsys, Inc. (Nasdaq:  SNPS) today announced that its IC Validator was successfully deployed on some of the industry’s largest and most advanced designs to accelerate design rule checking (DRC) closure. Through near-linear distributed processing and efficient resource management, IC Validator delivers industry-leading turnaround time, enabling physical signoff within hours on designs with 10 billion+ transistors. Technology advancements in the latest releases of IC Validator reduce both memory and disk usage requirements by 2x. This significant improvement in resource efficiency enables excellent performance scaling to several hundreds of CPUs by taking advantage of the smaller and more readily available machines in the customers’ existing compute farms.

“Increasing manufacturing complexity at advanced nodes makes it challenging for customers to complete physical signoff within schedule,” said Bijan Kiani, vice president, product marketing, Design Group at Synopsys. “Through high-performance scalability and readily available, optimized runsets from all major foundries, IC Validator is providing our customers with the fastest path to production silicon.”

IC Validator, part of the Synopsys Digital Design Platform, is a comprehensive and highly scalable physical signoff solution including DRC, LVS, programmable electrical rule checks (ERC), dummy fill and DFM enhancement. IC Validator is configured for today’s extremely large designs by enabling 8 CPUs with a single license. It uses both multi-threading and distributed processing over multiple machines to provide near linear scalability benefits that extend to several hundreds of CPUs. IC Validator enables coding at higher levels of abstraction and is architected for scalability to maximize utilization of mainstream hardware, using smart memory-aware load scheduling and balancing technologies.

IC Validator is a companion product to Synopsys IC Compiler™ II In-Design physical signoff. In-Design allows place-and-route engineers to perform independent signoff-quality analysis earlier, before the design is finalized and while correction can be automated. In-Design technology enables new high-productivity functionality within the place-and-route environment, including automatic DRC repair, improved timing quality-of-result with timing-aware metal fill, and rapid ECO validation. In-Design physical signoff eliminates expensive iterations with downstream analysis tools and maintains a convergent design flow to physical signoff.

Researcher team led by Professor Takayuki Ohba at Tokyo Institute of Technology, ICE Cube Center, in collaboration with the WOW (Wafer-on-Wafer) Alliance(term 2), an Industry-academic collaborative research organization consisting of multiple semiconductor related companies aiming for practical applications of 3D IC technology, demonstrated the thermal resistance of the 3D stacked device can be reduced down to less than 1/3 relative to the conventional one bonded by bump(term 3) 3D IC in Through-Silicon-Via (TSV) wiring(term 4). Since semiconductor circuits are highly heat-generating bodies during operation, when heat is hard to be released, the temperature of the semiconductor results in highly rise, which leads to be a malfunction. The development of heat dissipation technology has been a big challenge.

To address this challenge, Ohba and colleagues analyzed thermal properties in 3D IC using finite element method (FEM)(term 5) and thermal network calculation method. The study identified three main factors of thermal resistance; the interconnection layers, dielectric layers and organic layers in the conventional bump type device. Contrary to the bump type, the thermal performance of a bumpless 3D IC was almost 150 times better than that of a conventional IC at the same TSV density. The researchers demonstrated to reduce the total thermal resistance to 0.46 Kcm2/W, whereas the conventional method is 1.54 Kcm2/W. This suggests that the bumpless enables lower temperature rise and three to four times further DRAM stacking.

This is a cross-sectional structure of micro bump and bumpless. Credit: Tokyo Institute of Technology

This is a cross-sectional structure of micro bump and bumpless. Credit: Tokyo Institute of Technology

Based on their demonstration experiments, the scientists will work toward practical use of large-capacity memory technology for mobile terminals and servers.

Samsung Electronics Co., Ltd. announced today that its second generation 10-nanometer (nm) FinFET process technology, 10LPP (Low Power Plus), has been qualified and is ready for production. With further enhancement in 3D FinFET structure, 10LPP allows up to 10-percent higher performance or 15-percent lower power consumption compared to the first generation 10LPE (Low-Power Early) process with the same area scaling.

Samsung was the first in the industry to begin mass production of system-on-chips (SoCs) products on 10LPE last October. The latest Samsung Galaxy S8 smartphones are powered by some of these SoCs.

To meet long-term demand for the 10nm process for a wide range of customers, Samsung has started installing production equipment at its newest S3-line in Hwaseong, Korea. The S3-line is expected to be ready for production by the fourth quarter of this year.

“With our successful 10LPE production experience, we have commenced production of the 10LPP to maintain our leadership in the advanced-node foundry market,” said Ryan Lee, Vice President of Foundry Marketing at Samsung Electronics. “10LPP will be one of our key process offerings for high performance mobile, computing and network applications, and Samsung will continue to offer the most advanced logic process technology.”

According to the latest market study released by Technavio, the electrostatic discharge (ESD) packaging market is projected to grow to USD 5.42 billion by 2021, at a CAGR of more than 8% over the forecast period.

Global_ESD_Packaging_Market

This research report titled ‘ESD Packaging Market 2017-2021’ provides an in-depth analysis of the market in terms of revenue and emerging market trends. This market research report also includes up to date analysis and forecasts for various market segments and all geographical regions.

Communication network infrastructure

“The communication network infrastructure end-user segment occupies a significant 26% of the global ESD packaging market. The high rate of deployment of next-generation wireless networks such as Wi-Fi, WiMAX, 3G/4G, and ultra-wideband is responsible for the dominance of the market segment,” says Sharan Raj, a lead analyst at Technavio for packaging research.

The growth in the wireless network infrastructure market drives the demand for printed circuit boards (PCBs), which require ESD protection. Also, the increase in virtualization and cloud computing have resulted in increased Internet traffic worldwide, which is also indirectly boosting the market growth.

Consumer electronics industry

The consumer electronics segment includes smartphones, PCs, audio systems, video systems, and TVs, all of which incorporate sophisticated and high-performance printed circuit boards (PCBs) and semiconductors for efficient working. These electronic devices, combined with the rapid adoption of 3G and 4G networks, are driving the growth of ESD packaging in the market segment. Currently, APAC is showcasing an impressive growth curve in the market segment, driven by an extremely high mobile phone subscription rate.

Computer peripherals

“The computer peripherals segment is expected to reach a value of around USD 1,141 million by 2021. This segment includes products such as a mouse, keyboards, printers, hard drives, flash drives, scanners, webcams, and digital cameras which require ESD protection,” says Sharan.

This end-user segment is expected to be driven by the increased demand for tablets, notebooks, ultrabooks, and digital cameras. Further, the introduction of Windows 10 and lightweight ultrabooks will add a boost to the growth of the market segment.

The top vendors highlighted by Technavio’s research analysts in this report are:

  • BASF
  • Desco Industries
  • Dow Chemical
  • PPG Industries

Technavio is a global technology research and advisory company.