Category Archives: 3D Integration

Today, Transphorm Inc. announced that its second generation, JEDEC-qualified high voltage gallium nitride (GaN) technology is now the industry’s first GaN solution to earn automotive qualification—having passed the Automotive Electronics Council’s AEC-Q101 stress tests for automotive-grade discrete semiconductors.

Transphorm’s automotive GaN FET, the TPH3205WSBQA, offers an on-resistance of 49 milliOhms (mΩ) in an industry standard TO-247 package. The part initially targets on-board charger (OBC) and DC to DC systems for plug-in hybrid electric vehicles (PHEVs) and battery electric vehicles (BEV). Today, OBCs are uni-directional (AC to DC) using standard boost topologies. However, being that GaN FETs are bi-directional by nature, they become the perfect fit for the bridgeless totem-pole power factor correction (PFC) topology. Meaning, a bi-directional OBC can then be designed with GaN to reduce the number of silicon (Si) devices, weight and overall system cost of today’s solution.

“With the electrification of the automobile, the industry faces new system size, weight, performance, and cost challenges that can be addressed by GaN,” said Philip Zuk, Senior Director of Technical Marketing at Transphorm. “However, supplying this market means devices must meet the highest possible standards for Quality and Reliability, those set by the AEC. At Transphorm, we have a culture of Quality and Reliability. And, are proud to be leading the industry into the new era of in-vehicle power electronics.”

The automotive market is one of the fastest growing segments for all power semiconductors, with IHS Markit forecasting a $3 billion revenue by 2022. Due to its inherent attributes, Transphorm’s GaN can support a large portion of the market. When compared to incumbent tech such as superjunction MOSFETs, IGBTs and Silicon Carbide (SiC), those attributes include:

  • Up to 40 percent greater power density
  • Increased efficiency
  • Lower thermal budget
  • Reduced system weight
  • Up to 20 percent decrease in overall system cost
  • High volume manufacturing with 6-inch GaN on Silicon

As a result, Transphorm’s GaN can be used in other high voltage DC to DC automotive systems including air conditioning, heating, oil pumps and power steering.

Intel Corporation today announced that Omar Ishrak and Greg Smith have been elected to Intel’s board of directors.

“We are very pleased to welcome two new, independent directors with the depth of leadership experience at innovative, global companies that both Mr. Ishrak and Mr. Smith bring,” said Intel Chairman Andy Bryant. “We look forward to their valuable contributions as Intel continues to transform itself for growth in emerging, adjacent market segments.”

Omar-IshrakIshrak, 61, is the chairman and chief executive officer of Medtronic, a global leader in medical technology. He has served in that role since 2011. Prior to joining Medtronic, he spent 16 years in various roles with General Electric Company, most recently as president and chief executive officer of GE Healthcare Systems, a division of GE Healthcare. He is a member of the board of trustees of the Asia Society, which promotes mutual understanding and strengthening partnerships among peoples, leaders and institutions of Asia and the United States in a global context, and a member of the board of directors for Minnesota Public Radio.

Smith, 50, is the chief financial officer and executive vice president of corporate development and strategy at Boeing, the world’s largest aerospace and defense company. He has served as Boeing’s finance leader since 2012 and its strategy leader since 2015. Previously, Smith held various leadership roles across Boeing’s finance function and operations. He rejoined Boeing in 2008 after serving for four years as vice president of global investor relations at Raytheon. Smith serves on the board of trustees for the Chicago Museum of Science and Industry, and the board of directors of the Economic Club of Chicago, the Chicago Botanic Garden and the Northwestern Medicine Community Physicians Group.

At the SEMI Industry Strategy Symposium in Munich, SEMI announced recipients of the European SEMI Award for 2016: Rolf Aschenbrenner, deputy director of the Fraunhofer IZM; Eric Beyne, fellow and program director of 3D System Integration at imec; and Gilles Poupon, CEA fellow on advanced packaging and 3D integration at CEA-Leti. Since 1989, the European SEMI Award has been presented for significant contributions to the European semiconductor and related industries.  The three winners were nominated and selected by peers within the international semiconductor community in recognition of outstanding contributions in the field of 3D Integration.

“While the industry recognizes that SEMI Members imec, Fraunhofer and CEA-Leti are leaders in packaging technologies, the contributions of Rolf Aschenbrenner, Eric Beyne and Gilles Poupon and their teams are groundbreaking and advanced the semiconductor industry,” says SEMI Europe president Laith Altimime.

Rolf Aschenbrenner received a B.Sc. in mechanical engineering in 1986 and an M.Sc. in physics in 1991 from the University of Giessen. In 1994, he joined the Fraunhofer Institute for Reliability and Micro-integration in Berlin (IZM), where he is presently head of the department for chip interconnection technologies, and deputy director of the institute. Rolf Aschenbrenner’s research work spans from manufacturing process fundamentals to applied manufacturing problems. He has made substantial research contributions in thin and flexible electronic assemblies, end the development and analysis of innovative process technologies for all aspects of system level packaging. He served on various committees, and in 2013 he received the IEEE CPMT David Feldman Award.

Eric Beyne obtained a degree in electrical engineering in 1983 and a Ph.D. in Applied Science in 1990, both from the Catholic University Leuven. Since 1986, he has been employed at imec, where he works on advanced packaging and interconnect technologies. Currently, he is imec Fellow and programme director of imec’s 3D-integration programme. For more than ten years, Eric Beyne has been a pioneer in 3D system integration. He is a strong believer in the building of ecosystems in packaging and 3D, and has catalysed cooperation between IC-makers, designers, and Materials and equipment makers.

Gilles Poupon was educated at the University of Grenoble and the Conservatoire National des Arts et Métiers in Paris, where he received an M.Sc. in electrochemistry in 1985. He joined CEA-Leti in Grenoble in 1987. He became manager of the High Density Interconnect and Packaging Laboratory at Leti, where he was involved in the development of flip-chip technology, MEMS packaging and 3D-integration. Currently, he is programme manager on Advanced Packaging at CEA-Leti. Poupon is also a scientific advisor of the Eureka Initiative for Packaging and Integration of Microdevices and Smart Systems, and a member of various other committees involved in packaging and 3-D integration.

The European SEMI Award was established almost three decades ago to recognize individuals and teams who have made a significant contribution to the European semiconductor and related industries. Prior award recipients hailed from these companies: EV Group, Infineon, Semilab, Deutsche Solar, STMicroelectronics, imec, Fraunhofer Institute, and more.

Samsung Electronics Co., Ltd.today announced a successful network processor tape-out based on Samsung’s 14LPP (Low-Power Plus) process technology in close collaboration with eSilicon and Rambus. This achievement is built on Samsung’s cutting-edge foundry process and design infra for network applications, eSilicon’s complex ASIC and 2.5D design capability with its IP solutions, and Rambus’ high-speed 28G SerDes solution.

Samsung’s 14LPP process technology based on 3D FinFET structure has already been proven for its high performance and manufacturability through mass production track record. The next generation process for network application is 10LPP process which is based on 10LPE (Low-Power Early) of which mass production was started from last year for the first time in the industry. 10LPP process’ mass production will be started in this year end.

Additionally, Samsung named its newly developed full 2.5D turnkey solution, which connects a logic chip and HBM2 memory with an interposer, as I-CubeTM (Interposer-Cube) solution. This 14LPP network process chip is the first product that Samsung applied I-CubeTM solution together with Samsung’s HBM2 memory. The I-CubeTM solution will be essential to network applications for high-speed signaling, and it is expected to be adopted into other applications such as computing, server and AI in the near future.

“This successful 14nm network processor tape-out was combined with eSilicon’s proven design ability in network area and Rambus’ expertise in SerDes and Samsung’s robust process technology along with I-Cube solution,” said Ryan Lee, Vice President of Foundry Marketing Team at Samsung Electronics. “Our collaboration model will have a great influence on a network foundry segment and Samsung will keep developing its network foundry solution to be a meaningful total network solution provider aligned with its process roadmap from 14nm and 10nm to 7nm.”

“This project was a true collaboration between Samsung, Rambus and eSilicon. eSilicon is proud to bring its FinFET ASIC and interposer design skills along with our substantial 2.5D integration skills to the project,” said Patrick Soheili, Vice President of Product Management and corporate development at eSilicon. “Our HBM Gen2 PHY, custom flip-chip package design and custom memory designs also helped to optimize the power, performance and area for the project.”

“Networking OEMs are looking for high-quality leadership IP suppliers that can bring 28G backplane SerDes in advanced FinFET process nodes to market,” said Luc Seraphin, senior vice president and general manager of Rambus Memory and Interfaces Division. “Our success with Samsung and eSilicon is a testament that these industry-leading solutions are attainable when you bring leading companies together. This is the first of several other offerings we plan to bring to networking and enterprise ASIC markets around the globe.”

This article originally appeared on SemiMD.com and was featured in the March 2017 issue of Solid State Technology. 

By Dave Lammers, Contributing Editor

It takes a range of skills to create a successful business in the Internet of Things space, where chips sell for a few dollars and competition is intense. Circuit design and software support for multiple wireless standards must combine with manufacturing capabilities.

Daniel Cooley, senior vice president and general manager of IoT products at Silicon Labs (Austin, Tx.), said three trends are impacting the manufacture of IoT end-node devices, which usually combine an MCU, an RF transceiver, and embedded flash memory.

“There is an explosion in the amount of memory on embedded SoCs, both RAM and non-volatile memory,” said Cooley. Today’s multi-protocol wireless software stacks, graphics processing, and security requirements routinely double or quadruple the memory sizes of the past.

Secondly, while IoT edge devices continue to use trailing-edge technologies, nonetheless they also are moving to more advanced nodes. However, that movement is partially gated by the availability of embedded flash.

Thirdly, pre-certified system-in-package (SiP) solutions, running a proven software stack, “are becoming much more important,” Cooley said. These SiPs typically encapsulate an MCU, an integrated antenna and shielding, power management, crystal oscillators, and inductors and capacitors. While Silicon Labs has been shipping multi-chip modules for many years, SiPs are gaining favor in part because they can be quickly deployed by engineers with relatively little expertise in wireless development, he said.

“Personally, I believe that very advanced SIPs increasingly will be standard products, not anything exotic. They are a complete solution, like a PCB module, but encased with a molding compound. The SiP manufacturers are becoming very sophisticated, and we are ready to take that technology and apply it more broadly,” he said.

For example, Silicon Labs recently introduced a Bluetooth SiP module measuring 6.5 by 6.5 mm, designed for use in sports and fitness wearables, smartwatches, personal medical devices, wireless sensor nodes, and other space-constrained connected devices.

“We have built multi-chip packages – those go back to the first products of the company – but we haven’t done a fully certified module with a built-in antenna until now. A SiP module simplifies the go-to-market process. Customers can just put it down on a PCB and connect power and ground. Of course, they can attach other chips with the built-in interfaces, but they don’t need anything else to make the Bluetooth system work,” Cooley said.

“Designing with a certified SiP module supports better data throughput, and improves reliability as well. The SiP approach is especially beneficial for end-node customers which “haven’t gone through the process of launching a wireless product in in the market,” Cooley said.

Control by voice

The BGM12x Blue Gecko SiP is aimed at Bluetooth-enabled applications, a genre that is rapidly expanding as ecosystems like the Amazon Echo, Apple HomeKit, and Google Home proliferate.

Matt Maupin is Silicon Labs’ product marketing manager for mesh networking products, which includes SoCs and modules for low-power Zigbee and Thread wireless connectivity. Asked how a home lighting system, for example, might be connected to one of the home “ecosystems” now being sold by Amazon, Apple, Google, Nest, and others, Maupin said the major lighting suppliers, such as OSRAM, Philips, and others, often use Zigbee for lighting, rather than Bluetooth, because of Zigbee’s mesh networking capability. (Some manufactures use Bluetooth low energy (BLE) for point-to-point control from a phone.)

“The ability for a device to connect directly relies on the same protocols being used. Google and Amazon products do not support Zigbee or Thread connectivity at this time,” Maupin explained.

Normally, these lighting devices are connected to a hub. For example, Amazon’s Echo and Google’s Home “both control the Philips lights through the Philips hub. Communication happens over the Ethernet network (wireless or wired depending on the hub).  The Philips hub also supports HomeKit so that will work as well,” he said.

Maupin’s home configuration is set up so the Philips lights connect via Zigbee to the Philips hub, which connects to an Ethernet network. An Amazon Echo is connected to the Ethernet Network by WiFi.

“I have the Philips devices at home configured via their app. For example, I have lights in my bedroom configured differently for me and my wife. With voice commands, I can control these lamps with different commands such as ‘Alexa, turn off Matt’s lamp,’ or ‘Alexa, turn off the bedroom lamps.’”

Alexa communicates wirelessly to the Ethernet Network, which then goes to the Philips hub (which is sold under the brand name Philips Hue Bridge) via Ethernet, where the Philips hub then converts that to Zigbee to control that actual lamps. While that sounds complicated, Maupin said, “to consumers, it is just magic.”

A divided IoT market

IoT systems can be divided into the high-performance number crunchers which deal with massive amounts of data, and the “end-node” products which drive a much different set of requirements. Sandeep Kumar, senior vice president of worldwide operations at Silicon Labs, said RF, ultra-low-power processes and embedded NVM are essential for many end-node applications, and it can take several years for foundries to develop them beyond the base technology becoming available.

“40nm is an old technology node for the big digital companies. For IoT end nodes where we need a cost-effective RF process with ultra-low leakage and embedded NVM, the state of the art is 55nm; 40 nm is just getting ready,” Kumar said.

Embedded flash or any NVM takes as long as it does because, most often, it is developed not by the foundries themselves but by independent companies, such as Silicon Storage Technology. The foundry will implement this IP after the foundry has developed the base process. (SST has been part of Microchip Technology since 2010.) Typically, the eFlash capability lags by a few years for high-volume uses, and Kumar notes that “the 40nm eFlash is still not in high-volume production for end-node devices.”

Similarly, the ultra-low-leakage versions of a technology node take time and equipment investments, as well as cooperation from IP partners. Foundry customers and the fabless design houses must requalify for the low-leakage processes. “All the models change and simulations have to be redone,” Kumar said.

“We need low-leakage for the end applications that run on a button cell (battery), so that a security door or motion sensor, for example, can run for five to seven years. After the base technology is developed, it typically takes at least three years. If 40nm was available several years ago, the ultra-low-leakage process is just becoming available now.

“And some foundries may decide not to do ultra-low-leakage on certain technology nodes. It is a big capital and R&D investment to do ultra-low-leakage. Foundries have to make choices, and we have to manage that,” Kumar said.

The majority of Silicon Labs’ IoT product volume is in 180nm, while other non-IoT products use a 55nm process. The line of Blue Gecko wireless SoCs currently is on 90nm, made in 300mm fabs, while new designs are headed toward more advanced process nodes.

Because 180nm fabs are being used for MEMS, sensors and other analog-intensive, high-volume products, there is still “somewhat of a shortage” of 180nm wafers, Kumar said, though the situation is improving. “It has gotten better because TSMC and other foundries have added capacity, having heard from several customers that the 180nm node is where they are going to stay, or at least stay longer than they expected. While the foundries have added equipment and capital, it is still quite tight. I am sure the big MEMS and sensor companies are perfectly happy with 180nm,” Kumar said.

A testing advantage

IoT is a broad-based market with thousands of customers and a lot of small volume customizations. Over the past decade Silicon Labs has deployed a proprietary ultra-low-cost tester, developed in-house and used in internal back-end operations in Austin and Singapore at assembly and test subcontractors and at a few outside module makers as well. The Silicon Labs tester is much more cost effective than commercially available testers, an important cost advantage in a market where a wireless MCU can sell in small volumes to a large number of customers for just a few dollars.

“Testing adds costs, and it is a critical part of our strategy. We use our internally developed tester for our broad-based products, and it is effective at managing costs,” Kumar said.

The technology leader in the DRAM industry has a greater advantage in terms of market share and profit.

BY HEISEUNG KIM and HEESANG LEE, Management of Technology Department at Sungkyunkwan University, Suwon, South Korea

This paper presents an empirical study that links between firms’ technological leadership and the firms’ sustainability. While extant studies focused on the effect of incremental or radical innovation on the firm, a few researches have been carried out on the other types of innovation. In this study, architecture innovation in the DRAM industry is used to analyze how the continuous archi- tecture innovation of scaling affects firms’ performance. We compared the historical technology roadmap of each firm with their market share and profit data and concluded that continuous architecture innovation would positively affects the performance of a firm as well as its chance of survival. This study suggests that continuous architecture innovations are required in order to stay competitive in DRAM industry.

Introduction

Invented by Robert Dennard at IBM in 1966, Dynamic Random Access Memory (DRAM) is one of the major types of semiconductor products. Since then, the DRAM market has grown significantly, accounting for $45.1 billion in sales in 2015 [1]. The DRAM industry has three main and crucial industry characteristics: product life cycle is short, it is technology driven, and it requires a huge investment [2]. The average DRAM product life cycle is about two to three years and the capacity ranges increased from 4K DRAM in 1974 to 2G DRAM in 2010. The implication of the short product life cycle is that the DRAM manufacturer with technology leadership will be able to recover their initial investment and gain more profit; therefore, the DRAM industry is highly driven by technology [3]. The technology leader can earn premium profit at the initial stage of a new product and benefit from additional profit by sustainability in the grown market. However, technology followers can suffer from price reduction when they launch a new product due to the mature state of a product life cycle, and it might thus be difficult to recover their initial investment [4]. The production of DRAM requires numerous steps with very expensive equipment; the cost of a new semiconductor fab is billions of dollars; a proper analysis and suitable strategy is therefore needed in order to compete with other comparative companies in the industry. In 1991, there were more than dozen DRAM production firms. However, by 2012, only four major companies survived: Samsung, SK Hynix, Elpida, and Micron [1].

The well-known scaling law of semiconductors, known as Moore’s Law, was used to review the technology development process in the semiconductor industry [5]. Recently, many researchers, including Mack and Kim, have argued that, even though Moore’s Law provided considerable insight into the semiconductor industry, it is no longer valid; they added that the physical and technical limitation will slow down the innovation and breakthrough technologies are necessary in the semiconductor industry [3-4,6]. Therefore, many companies and researchers are focusing on developing new memory devices, such as Magnetic RAM (MRAM) and Phase-change RAM (PRAM), to replace current DRAM memory. However, it is not clear how and when are the right time to replace the current DRAM memory with new memory devices and how it might affects the firms’ business performance [5,7-8]. In this paper, we will discuss how continuous architecture innovation affects the performance of DRAM companies in terms of market share and profit.

Innovation types

In the long run, technological innovation capabilities are the major source of competitive advantage and many companies are pursuing extensive research activities in order to stay competitive in the market [9]. The ability to develop and introduce new products or processes in shorter time periods is inevitable and has become the major competence for firms [10].

Henderson and his colleagues defined the types of innovation as four categories: incremental, archi- tecture, modular, and radical innovation [11], defined as follows:
• Incremental innovation: innovation with no change in architecture and concept.
• Architecture innovation: innovation with new archi- tecture but without change in concept.
• Modular innovation: fundamental change of techno- logical concept without change in architecture.
• Radical innovation: new architecture and new concept.
ByusingHenderson’sdefinition,thetypesofinnovation in the DRAM industry can be defined as shown in TABLE 1. In this paper, we will focus on the archi- tecture innovation which is the major innovation in DRAM industry [3,5].

Screen Shot 2017-04-20 at 10.11.44 PM

Market leadership and profit relationship

Many firms attempt to improve their performance through innovation and according to recent study by Bowen and his colleagues the relationship between innovation and the future performance of the firm is positive [12]. For many firms, including DRAM manufactures, maintaining a leadership position in the industry is a major goal because the duration of the stay at the top of the market reflects the length of time they might be able to enjoy the benefits as a market leader [13]. Therefore, a study is needed on the relationship between the market leader and the followers in terms of profits. In the case of the DRAM industry, the forces of competition are high and there are no room for slow followers to stay profitable; winner takes it all.

Continuous development

Van Valen introduced a theory known as the Red Queen Effect which states that competition will eliminate less fit organizations and stimulate organizational learning [14]. Therefore, continuous innovation is needed in order to maintain fitness relative to the system [15]. This theory explains the continuation of the never ending arms race which is due to the initial innovation of a firm which not only increases its competitiveness, but also decreases the competitiveness of its rivals. The rivals are threatened by an increased competitive pressure, and will respond to a competitor’s innovation with their own innovation, which then increases the competitive pressures in the market, creating a continual cycle of competitiveness [16]. The same theory is valid when assessing competitiveness in the DRAM industry. In 2007, the production by firms in the DRAM industry greatly increased, initiating a price war between the companies, known as the Chicken Game. After 2007, the price of DRAM dropped and DRAM manufacturers underwent a severe decrease in profits [1]. Those who prepared for this race were able to endure the race. However, those who were not prepared and decided to cut production could not withstand the massive supply of DRAM; such companies included Elpida, which lost its position as a leader in the more advanced technology. Their economies of scale reduced and due to the severe deficit, they lost their business and merged with Micron in 2013.

Screen Shot 2017-04-20 at 10.11.51 PM

Methodology and data

For the DRAM industry, the market share of the top four companies is about 95% of the total industry’s market share therefore the force of competitions and innovation-performance relationship are well repre- sented by these four companies. The market share and OPM data of the top four companies, Samsung, SK Hynix, Elpida, and Micron, were used in this study and the market share data was refined to represent only these four companies [1]. The data from third quarter of 2006 to 2012 is used because chicken game started at 2007 and Elpida was merged to Micron at 2013. For the companies’ historical product roadmap, development histories of different nodes were obtained from each company’s press releases. For the statistical data of the market share and the operating profit margin (OPM) was obtained from market research firm, IHS isuppli.

Results and discussions

FIGURE 1 shows the trend of the market share change in terms of companies’ historical roadmaps in the DRAM industry. The same numbers of color, 6x, 5x, 4x, 3x 2x nm, indicates the same device generations of architecture innovation and showing the technology gap among firms. For example, Samsung’s 68nm node is competing with SK Hynix’s 66nm and SK Hynix is one quarter behind than Samsung. As expected, the market share of the technology leader, Samsung, is the highest. Samsung has the highest market share of slightly above 40% and SK Hynix has about 25%. Elpida and Micron both have a market share of about 15%. Also, the market share of the technology leader increased as Samsung managed to develop next node product faster than competitors. Technology ranking exactly matches the market share ranking and Samsung was able to maintain their technology and market leadership.

Screen Shot 2017-04-20 at 10.11.59 PM

FIGURE 2 shows the profit ranking among the DRAM manufactures in terms of device generations. Profit might be more important factor than market share for the firms’ sustainability since it is directly connected to the firms’ survival as seen during the chicken game. Samsung, the market and technology leader, shows the highest Operating Profit Margin (OPM). The profit ranking changed once for Samsung in the second quarter of 2007, during the chicken game. After the second quarter of 2007, Samsung retained the title of the most profitable firm in the DRAM industry. However, there were many fluctuations for the firms that ranked second and less. During 2007 to 2012, Samsung had a negative profit quarter five times [1]. This is very low compared to the 12 times shown by the second leader, SK Hynix, 16 times by Elpida, and 17 times by Micron.

Screen Shot 2017-04-20 at 10.12.05 PM

A previous study by Weber and Yang suggested that in semiconductor industry while leading edge manufac- turers make large profits, but their ROI (Return On Investment) might be lower than the slow followers [17]. This might be true for logic semiconductor devices, since the logic firms produce much specified products and, most of the time, the competitiveness of such firms does not derive from the most advanced scaling node or continuous architectural innovation; rather it derives from optimization, design, and customer value. However, for the DRAM industry, the effect of logic’s competitiveness is limited since the price of DRAM, as a commodity, is determined by the market and the main competitiveness is how many bits that firms can produce in a restricted area of 300nm wafers. Therefore, slow follower probably not able to compete in the market in terms of price.

TABLE 2 shows the ranking data of Samsung from third quarter of 2006 to 2012. Samsung, the market and technology leader was able to manage to stand at the top in terms of technology and market share. In terms of profit, Samsung ranked 2nd only for one quarter in 2007 and managed to return 1st rank due to techno- logical advantage. This result suggests that Samsung was able to maintain its position even during the chicken game and was able to stay fit in the market and make profit compared to the other companies. In the case of the DRAM industry, continuous architecture innovation means that the number of chips per wafer would increase as innovation succeeded. The delayed development of the next generation device would lead to SK Hynix, Elpida, and Micron producing fewer DRAM chips per wafer than Samsung, which led to the increase of the DRAM manufacturing cost. Staying competitive in the market by continuous architecture innovation is most important for DRAM manufac- turers’ as it enables more profit to be made than the competitors; Elpida could not stand the large amount of deficit and merged to Micron.

Conclusions

In this study, the benefits of being the technology leader of architecture innovation in the DRAM industry are clearly shown, where the technology leader has a greater advantage in terms of market share and profit than the competitors. Also, the technology leader has more resilience when the industry is undergoing a difficult time, and would be able to perform better than other firms. The firms that do not continue to innovate will not survive. In 2002, 11 DRAM manufac- turers were competing intensely in the market; however currently, only 3 major DRAM manufacturers had survived. Many large firms such as Qimonda and Elpida failed to survive. The critical factor which deter- mines the ability to dominate in the DRAM industry is continuous architecture innovation. For example, EUV lithography is necessary for continuous architectural innovation since the next scaling node will require smaller patterning with multi-patterning of ArF, which needs many additional steps and processes than EUV process. However, the application of a 450mm sized wafer is not considered as an architectural innovation since the 450nm wafer does not improve the structure of the device. Therefore, it is considered an incremental innovation for the DRAM industry; the 450nm sized wafer is not urgent and not yet required. This study provides understanding for firms to suggest which technology that they need to focus on in order to stay competitive in the market in the future.

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Synopsys, Inc. (Nasdaq:  SNPS) today announced that TSMC has certified the complete suite of products in the Synopsys Galaxy Design Platform for the most current version of 12-nanometer (nm) FinFET process technology. This 12nm certification brings with it the broad body of design collateral, including routing rules, physical verification runsets, signoff-accurate extraction technology files, SPICE correlated timing and interoperable process design kits (iPDKs) for this latest FinFET process. Synopsys Custom Compiler design solution support is enabled through an iPDK.

To accelerate access to this power-efficient, high-density process, IC Compiler II place-and-route system has been enabled to support new standard cell architectures seamlessly co-existing with 16FFC intellectual property (IP). Recent collaborations have resulted in enhancements to IC Compiler II’s core placement and legalization engines ensuring maximum utilization while minimizing placement fragmentation and cell displacement. The 12nm ready iPDK enables designers to use Custom Compiler’s layout assistant features to shorten time in creating FinFET layouts.

“This power-efficient, high-density node offers a broad set of opportunities to our customers, enabling them to deliver highly differentiated products,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “Our ongoing collaboration with Synopsys is helping expedite designer access to 12-nm process technology.”

“The long-standing collaboration between Synopsys and TSMC continues to be key in bringing accelerated access to new process technology nodes,” said Bijan Kiani, vice president of product marketing for the Design Group at Synopsys. “With the Galaxy Design Platform certified for 12nm readiness, our mutual customers are enabled to speed up development and deployment to accelerate their time-to-market.”

Synopsys, Inc. (Nasdaq:  SNPS) today announced its collaboration with TSMC to develop DesignWare Interface, Analog and Foundation IP for TSMC’s 12FFC process. By offering a wide range of IP on TSMC’s latest low-power process, Synopsys is enabling designers to take advantage of the low leakage and small area advantages of the new process. Synopsys and TSMC have partnered on the development of Synopsys IP for advanced process technologies for more than two decades, resulting in a robust portfolio of IP supporting process technologies down to 7nm. Synopsys DesignWare IP for the 12FFC process enables designers to accelerate development of mobile SoCs that incorporate logic libraries, embedded memories, embedded test and repair, USB 3.1/3.0/2.0, USB-C 3.1/DisplayPort 1.3, DDR4/3, LPDDR4X, PCI Express 4.0/3.1/2.1, SATA 6G, HDMI 2.0, MIPI M-PHY and D-PHY and data converter IP.

“TSMC and Synopsys share a long history of providing designers with a wide range of high-quality IP on TSMC’s advanced FinFET processes,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “By developing IP on the latest TSMC 12FFC process, Synopsys is paving the way for designers to improve their SoCs’ leakage and lower overall costs.”

“As SoCs continue to incorporate more advanced functionality, designers are constantly challenged with meeting aggressive performance, power and area requirements,” said John Koeter, vice president of marketing for IP at Synopsys. “Our close collaboration with TSMC on the development of a broad range of IP for the 12FFC process will ensure that designers have timely access to the high-quality, proven IP solutions they need to achieve their design goals and quickly get their product to market.”

Synopsys is a provider of high-quality, silicon-proven IP solutions for SoC designs.

STATS ChipPAC Pte. Ltd., a provider of advanced semiconductor packaging and test services, announced today that it has shipped 1.5 billion fan-out wafer level packages (FOWLP), also known in the industry as embedded Wafer Level Ball Grid Array (eWLB).  In high volume production for over seven years, STATS ChipPAC has led the industry in FOWLP technology innovations and unit shipments.

“As an early adopter of FOWLP, STATS ChipPAC set an aggressive course in pushing the boundaries of advanced package architecture and manufacturing capabilities long before its peers. We have delivered a number of breakthrough achievements in package density, form factor and heterogeneous integration while continually driving innovations in the manufacturing process to provide a proven, cost effective advanced packaging platform for our customers,” said Shim Il Kwon, Chief Technology Officer, STATS ChipPAC. “Shipping 1.5 billion eWLB packages is a testament to the growing adoption of this technology and the performance, size and cost advantages it provides to our customers.”

FOWLP or eWLB is an advanced packaging technology platform that provides ultra-high density interconnection, superior electrical performance and the ability to integrate multiple heterogeneous dies in a cost effective, low-profile semiconductor package. STATS ChipPAC has a comprehensive portfolio of eWLB package designs, including small die, large die, multi-die, multi-layer, Micro-Electro-Mechanical Systems (MEMS), 2.5D and 3D Package-on-Package (PoP) and System-in-Package (SiP) architectures. A number of eWLB technology milestones have been driven by STATS ChipPAC such as dense vertical interconnections as high as 500 – 1,000 I/O, very fine line width and spacing down to 2um/2um and ultra-thin package profiles below 0.3mm (including solderball) for single packages and below 0.6mm for a stacked PoP with proven warpage control.

Although there are multiple variations of fan-out packaging in development in the industry, eWLB is the only FOWLP solution in the market today that has been in high volume manufacturing for over seven years. STATS ChipPAC has been instrumental in driving important optimizations in the manufacturing process and infrastructure. The eWLB manufacturing process has evolved into the innovative FlexLineTM manufacturing method which was introduced and implemented by STATS ChipPAC in 2014.  The FlexLineTM method delivers unprecedented flexibility in producing both fan-out eWLB and fan-in wafer level chip scale packages (WLCSP) on the same manufacturing line for higher economies of scale and lower cost.

“The depth of production experience we have gained over the years has enabled STATS ChipPAC to continually refine and optimize the eWLB manufacturing process to drive higher output and lower cost per unit. We have made significant capital investments over the years to expand our capacity and continue to increase our production volume to support growing customer demand,” said Cindy Palar, Managing Director, STATS ChipPAC Singapore. “Our 1.5 billion unit milestone reflects the confidence our customers have in eWLB technology and our ability to deliver an advanced packaging solution that best meets the cost and performance targets for their product requirements.”

Currently all leading mobile products as well as some consumer electronics contain eWLB packages that are baseband processors, RF transceivers, connectivity devices, near field communication (NFC), security devices, MCUs, memory, memory controllers, RF MEMS and power management ICs (PMICs). The compelling performance, integration and size advantages of eWLB are also accelerating customer adoption in new and emerging market segments such as the Internet of Things (IoT), wearable electronics, millimeter wave (mmWave) technology for 5G wireless devices, MEMS and sensors, and automotive applications such as Advanced Driver Assistance Systems (ADAS).

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced several new capabilities resulting from its close collaboration with TSMC to further 7nm FinFET design innovation for mobile and high-performance computing (HPC) platforms. The Cadence digital, signoff and custom/analog tools have achieved certification for v1.0 Design Rule Manual (DRM) and SPICE certification for the TSMC 7nm process. Cadence has also delivered solutions for a new process design kit (PDK) enabling optimal power, performance and area (PPA) when designing with TSMC’s 7nm process. In addition, the Cadence 7nm Custom Design Reference Flow (CDRF) and the library characterization flow have been enhanced, and its 7nm DDR4 PHY IP is in deployment with customers.

7nm Tool Certification Cadence provides a fully integrated digital flow from implementation to final signoff that has been certified by TSMC for the 7nm process. The digital flow includes the Innovus Implementation System, Quantus QRC Extraction Solution, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution, Voltus-Fi Custom Power Integrity Solution, Physical Verification System (PVS) and Layout-Dependent Effect (LDE) Electrical Analyzer.

Support for TSMC’s 7nm HPC platform includes via-pillar modeling in the Genus Synthesis Solution and full via-pillar-capable implementation and signoff environments. Additionally, clock-mesh handling and bus-routing capabilities in the tools support the high-performance library to deliver better PPA and mitigated electromigration (EM). These capabilities enable customers to successfully design advanced-node systems while reducing iterations and achieving cost and performance objectives.

The certified custom/analog tools include the Spectre Accelerated Parallel Simulator (APS), Spectre eXtensive Partitioning Simulator (XPS), Spectre Classic Simulator, Virtuoso Layout Suite, Virtuoso Schematic Editor, and Virtuoso Analog Design Environment (ADE). Enhancements made for the 7nm process include advanced device snapping and an accelerated custom placement and routing flow that enables customers to improve productivity and meet power, multiple patterning, density and EM requirements.

7nm CDRF Delivery Cadence delivered an enhanced Custom Design Reference Flow (CDRF) to address 7nm custom and mixed-signal design challenges. The CDRF incorporates advanced methodologies and features that provide productivity improvements through a series of in-depth “how-to” circuit design, layout implementation, and signoff and verification modules. The circuit design module covers “how-to” topics, such as capturing schematics with device arrays using module generator (ModGen) constraints and the TSMC PDK, functional verification, yield estimation and optimization, and the latest reliability analyses. For signoff verification, the physical verification modules highlight design rule and layout-versus-schematic (LVS) checking, signoff parasitic extraction, and electromigration and IR drop (EM/IR) signoff checks.

The layout implementation module includes connectivity and constraint-driven layout for FinFET device placement, enabling designers to avoid design rule violations and address layout-dependent effects (LDEs). The routing module offers a color-aware flow and an innovative track-pattern system that reduces design time, mitigates parasitics and helps designers avoid EM issues.

7nm Library Characterization Tool Flow Delivery In addition to tool certification, the Cadence Virtuoso Liberate Characterization Solution and the Virtuoso Variety Statistical Characterization Solution have been validated to deliver Liberty libraries for the TSMC 7nm process including advanced timing, noise and power models. The solutions utilized innovative methods to characterize the Liberty Variation Format (LVF), enabling process variation signoff and the ability to create EM models enabling signal EM optimizations and signoff.

7nm IP Collaboration As a leader in DDR controller and PHY IP, Cadence has deployed its DDR4 PHY and LPDDR4 PHY in multiple generations of TSMC process technologies, ranging from 28HPM/28HPC/28HPC+ to 16FF+/16FFC nodes. Through close collaborations with TSMC and customers, Cadence began developing IP on the 7nm process last year. Cadence has taped out its flagship DDR4 PHY using the 7nm process node in Q4 2016, and key customers have integrated the 7nm DDR PHYs into their enterprise-class SoCs.

“TSMC’s latest process advancements combined with enhancements to Cadence tools and IP offer our mutual customers optimal solutions for advanced-node designs,” said Dr. Anirudh Devgan, executive vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “This certification and the v1.0 process maturity milestone represent our readiness to meet the production needs of our most innovative customers using the 7nm process.”

“The availability of new v1.0 design rules and PDK indicates that we’ve reached a new pinnacle with 7nm production designs,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “We’ve collaborated closely with Cadence to certify its tools and deliver IP innovations for 7nm designs, which enable our customers to achieve their PPA objectives with mobile and HPC designs.”

“ARM has collaborated closely with Cadence and TSMC to enable a 7nm design flow for our joint customers,” said Monika Biddulph, general manager of the Systems and Software Group, ARM. “This flow is enabling the development of platforms for high-end mobile and high-performance computing applications.”