Category Archives: 3D Integration

By Dr. Phil Garrou, Contributing Editor

walkerJim Walker, who retired from Gartner and is now consulting as World Level Packaging Concepts, gave a plenary talk at the recent IMAPS Device Packaging Conference in Scottsdale on the state of the semiconductor industry which contained some interesting perspectives on emerging new business models.

While Gartner 2020 projections show wireless and computer will still account for ~ 50% of the overall market activity, automotive, storage and industrial will show significant growth (7-9%) between now and then and account for ~ 30% of the total market (combined).

Gartner expects consolidation to continue “…with semi companies sitting on $135B in cash and profit margins decreasing there is a need to diversify into new markets” with specifics including:

– IoT related M&A activity will drive consolidation in MCU, analog and sensor technologies.

– Companies will initiate sale of unprofitable divisions and product lines to prepare themselves for M&A (i.e. make themselves more attractive to be acquired).

– China will continue to buy or invest in U.S. and European companies, even as governments impose restrictions.

5 Year Revenue Growth for Application Markets [source: Gartner]

5 Year Revenue Growth for Application Markets [source: Gartner]

Gartner sees the industries maturation resulting in traditional business models changes. The traditional semiconductor ecosystem is shown below.

The Semiconductor Ecosystem

The Semiconductor Ecosystem

Gartner reports that a relatively new problem for some OEMs and Electronics Brands is that they are being bypassed by a direct relationship between the ODM/EMS Co. and a non- electronics brand owner buyer who could be in any industry. This model emerged with Operator branded handsets, although those were recognizable as say Nokia or Motorola. This (Brand) Direct to ODM/EMS business model is good for chip suppliers but bad for traditional electronics companies.

walker 3B

Another relatively new problem for some chip companies now is that they are being bypassed by a direct relationship between the foundry and the EMS/ODM company and the OEM –the OEM Direct model. These could be chips designed by Apple or Facebook (for example) and manufactured by TSMC.

walker 4

Walker specifically suggests we keep an eye on Hon Hai / Foxconn who appears to be building strong and broad manufacturing capabilities through acquisitions like Japans Sharp (Feb 2016) and bidding on the Toshiba memory business (2017).

Packaging is currently ~17% ($53B) of the $265B electronics market. By 2020, 55% of all packaging is expected to be done at OSATS with foundries like TSMC (and maybe others soon) becoming competitors with their own wafer based packaging offerings like InFO. Walker sees a bright future for IoT packaging, but cautions that it is composed of many small to mid sized applications, not one big one like the smart phone, and thus will require many custom packaging solutions.

Cadence Design Systems, Inc. (NASDAQ:  CDNS) today announced new optimization capabilities within its holistic, integrated design flow for TSMC’s advanced wafer-level Integrated Fan-Out (InFO) packaging technology. The integrated flow provides design and analysis capabilities and modeling of cross-die interactions for mobile and IoT applications.

The Cadence tools in the enhanced flow include the OrbitIO interconnect designer, System-in-Package (SiP) Layout, Quantus QRC Extraction Solution, Sigrity XtractIM technology, Tempus Timing Signoff Solution, Physical Verification System (PVS), Voltus-Sigrity Package Analysis, Sigrity PowerDC technology and Sigrity PowerSI 3D-EM Extraction Option. With the new flow, system-on-chip (SoC) designers can:

  • Quickly generate netlists among the multiple dies and InFO package in the context of the full system within a single-canvas multi-fabric environment: The OrbitIO interconnect designer efficiently handles multi-die integrations with TSMC InFO technologies to generate top-level netlists that can be directly used for subsequent design steps such as detailed electrical and timing analysis.
  • Generate Standard Parasitic Exchange Format (SPEF) directly from the package design database, which greatly eases timing signoff: Rather than using a traditional methodology that requires converting the package design database of an InFO design to an IC design database to generate SPEF, Sigrity XtractIM technology automatically generates SPEF for heterogeneous InFO systems, which accelerates the timing signoff process and speeds time to market.

“We’ve continued to see strong demand from mobile and IoT customers who want to deploy systems based on TSMC’s InFO technology,” said Steve Durrill, senior product engineering group director at Cadence. “By working closely with TSMC, we are enabling our mutual customers to shorten design and verification cycle times so they can deliver reliable, innovative SoCs to market faster.”

“The Cadence flow developed specifically for our InFO technology is an enabler for customers who need to increase bandwidth within small form factors,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “The integrated full-flow includes a comprehensive set of Cadence digital, signoff and custom IC technologies that address this market need, and our collaboration is helping customers to efficiently achieve their design goals.”

NXP Semiconductors N.V. (NASDAQ:NXPI) today announced the world’s smallest single-chip SoC solution – the MC9S08SUx microcontroller (MCU) family – with an integrated 18V-to-5V LDO and MOSFET pre-driver that delivers ultra-high-voltage solution for drones, robots, power tools, DC fan, healthcare and other low-end brushless DC electric motor control (BLDC) applications. Extending the company’s S08 family of MCUs, the robust 8-bit MC9S08SUx microcontroller family offers 4.5V~18V supply voltage range with lower bill of materials (BOM) cost and tighter integration for higher performance and reliability. The new SoC units address the growing demand to replace multiple device solutions with a single MCU to reduce cost and system size, while simplifying integration and layout for space-constrained use cases.

“The market trend is pointing towards integrated solutions that save system size and cost, and NXP is leading the industry as the only provider to offer a single-chip offering with integrated microcontroller and MOSFET pre-driver in a 4x4x0.65mm form factor, which also makes it possible to cut the printed circuit board size in half,” said Geoff Lees, senior vice president and general manager of the microcontroller business line at NXP. “Historically, several devices were needed to address the needs of BLDC motor control applications, which can be expensive and large in size; our latest addition to the S08 MCU family underscores our dedication to solving unique challenges by introducing new microcontrollers for the broad market.”

Based on the HCS08 core, the MC9S08SUx leverages the enhanced S08L central processor unit with three-phase MOSFET pre-drivers to deliver all-in-one unit for 4.5V-18V motor control applications. The single-chip MC9S08SUx MCU removes the need for Low Drop Out (LDO) voltage regulator(s), operational amplifiers, and pre-drivers for a streamlined, cost-effective solution. Additionally, NXP has integrated virtually all of the necessary features in BLDC motor control, including zero crossing point detection, pulse width measurement, over voltage protection and over current protection, enabling developers to simply configure registers and easily use the functions in applications. The MC9S08SUx family also includes amplifiers for current measurement and supports three high-side PMOSes as well as three low-side NMOSes.

NXP’s S08 microcontrollers, including the new MC9S08SUx family, are supported by CodeWarrior IDE. FreeMASTER support is offered as run-time debugging tool. In addition, IAR Embedded Workbench supports the NXP S08 MCU portfolio, offering a single toolbox complete with configuration files, code examples and project templates. IAR Embedded Workbench support for the MC9S08SUx MCU family will be available March 2017.

“The leading optimization technology in IAR Embedded Workbench helps developers to maximize performance and minimize power consumption for applications based on the new MC9S08SUx MCU family from NXP,” said Jan Nyrén, Product Manager, IAR Systems.

Eutelsat Communications (NYSE Euronext Paris: ETL),a satellite operator, and STMicroelectronics (NYSE: STM) have achieved a new milestone with a new-generation chip that will power Eutelsat’s SmartLNB interactive terminal.

ST’s advanced, low-power System-on-Chip (STiD337) represents a big step down in the overall cost of interactive satellite terminals. The STiD337’s first adoption is in Eutelsat’s SmartLNB, lowering cost, upgrading service, and significantly reducing power consumption.

The SmartLNB is an electronic feed that replaces the traditional Ku-band reception of DTH satellite signals, embedding one or more satellite tuners/demodulators directly inside the LNB (low-noise block) and adding a narrowband return link optimized for transmissions of IP packets. The SmartLNB enables a wide range of connected TV applications, providing a transparent bidirectional IP link compatible with existing services. Not limited to the TV and broadcast market, applications also cover the exploding sector of connected objects (Machine-to-Machine, Internet of Things, SCADA, home-automation, Smart Buildings, etc.) with a cost-effective solution via satellite.

ST has employed its very low-power 28nm FD-SOI (Fully Depleted Silicon on Insulator) process technology that enables deep sleep and auto wake up for the system. With a maximum 3.5W power dissipation at full speed and less than 50mW (typical) during sleep, the STiD337 is the most power-efficient device available today to take the SmartLNB to a new level of performance and efficiency.

The STiD337 adds the latest DVB-S2X satellite standard for the forward link, as well as GSE (Generic Stream Encapsulation) for efficient data handling; it can achieve throughput of over 100Mb/sec. The return path implements a software-radio approach that is optimized for the enhanced spread-spectrum technique with asynchronous access typically used for the SmartLNB. The device also includes the full complement of hardware mechanisms to support real-time multiple-access techniques. The return modulation is calculated on the internal processors. The platform includes a dual ARM Cortex-A9 core with NEON co-processors and four ST231 DSP offload coprocessors to enhance its compute power and ensure complete flexibility in the choice of return-channel modulation type.

The new SoC will be available in secure and standard versions. The secure version includes pre-loaded encryption keys, serial numbers, safe-boot, and many other features to increase the level of protection of data-delivering and gathering operations by the SmartLNB.

“We wanted a step change in the cost and performance for the next generation of our SmartLNB interactive service. We know from our customers that security is a major concern and we wanted to address that head on. Furthermore, with satellite terminals becoming more ubiquitous and employed in a greater range of use cases we needed to pay even greater attention to power consumption,” said Antonio Arcidiacono, Director of Innovation at Eutelsat. “The design objectives we set have all been met and we’re aiming to roll out higher-performance, lower-cost, secure, and above all, lower-power consumption SmartLNB terminals based on ST’s new satellite SoC by the end of 2017.”

“Working closely with Eutelsat, we’ve developed the lowest-cost, lowest-power, secure, and most advanced interactive satellite-modem SoC to date,” said Jocelyne Garnier, Group VP, General Manager, Aerospace, Defense, and Legacy Division, STMicroelectronics. “From the outset we knew we could bring innovations to the market that played to many of the strengths we have in ST, especially in digital satellite systems, our system-on-chip experience, our low-power technologies, and of course, our security IP.”

ST provides a hardware evaluation platform, a Linux-based operating system, and a basic driver set. Final production samples of the STiD337 are available now and full production is scheduled for May 2017. Further information is available on ST.com and under NDA.

The Semiconductor Industry Association (SIA) today announced worldwide sales of semiconductors reached $30.6 billion for the month of January 2017, an increase of 13.9 percent compared to the January 2016 total of $26.9 billion. Global sales in January were 1.2 percent lower than the December 2016 total of $31.0 billion, reflecting normal seasonal market trends. January marked the global market’s largest year-to-year growth since November 2010. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“The global semiconductor industry is off to a strong and encouraging start to 2017, posting its highest-ever January sales and largest year-to-year sales increase in more than six years,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Sales into the China market increased by more than 20 percent year-to-year, and most other regional markets posted double-digit growth. Following the industry’s highest-ever revenue in 2016, the global market is well-positioned for a strong start to 2017.”

Year-to-year sales increased substantially across all regions: China (20.5 percent), the Americas (13.3 percent), Japan (12.3 percent), Asia Pacific/All Other (11.0 percent), and Europe (4.8 percent). Month-to-month sales increased in Europe (1.2 percent), but fell slightly in China (-0.2 percent), Japan (-1.6 percent), Asia Pacific/All Other (-1.6 percent), and the Americas (-3.1 percent).

January 2017

Billions

Month-to-Month Sales                               

Market

Last Month

Current Month

% Change

Americas

6.33

6.13

-3.1%

Europe

2.80

2.84

1.2%

Japan

2.84

2.79

-1.6%

China

10.17

10.15

-0.2%

Asia Pacific/All Other

8.86

8.72

-1.6%

Total

31.01

30.63

-1.2%

Year-to-Year Sales                          

Market

Last Year

Current Month

% Change

Americas

5.41

6.13

13.3%

Europe

2.71

2.84

4.8%

Japan

2.49

2.79

12.3%

China

8.42

10.15

20.5%

Asia Pacific/All Other

7.86

8.72

11.0%

Total

26.89

30.63

13.9%

Three-Month-Moving Average Sales

Market

Aug/Sept/Oct

Nov/Dec/Jan

% Change

Americas

6.06

6.13

1.2%

Europe

2.82

2.84

0.7%

Japan

2.89

2.79

-3.2%

China

9.78

10.15

3.7%

Asia Pacific/All Other

8.88

8.72

-1.8%

Total

30.43

30.63

0.7%

 

At the CS International Conference (Brussels, March 7-8), imec will present promising device results with a InGaAs-only TFET (tunnel field-effect transistor). Achieving a sub-60 mV/decade sub-threshold swing at room temperature, these devices are promising candidates to replace MOSFET transistors in future chip generations for ultralow-power applications operating on ultralow supply voltages.

TFETs exploit a different mechanism to inject carriers than MOSFETs, the most dominant transistor type today. While MOSFETs introduce carriers from the source into the conducting channel by thermal injection, a TFET works through band-to-band tunneling (BTBT). With that, they promise sub-threshold swings smaller than 60mV/dec, which is below the limit of what is possible with MOSFETs. This would allow operating them at ultralow supply voltages (below 0.5V).

The device developed at imec is an InGaAs homojunction TFET. It shows a minimum sub-threshold swing of 54mV/dec at 100pA/mm. The sub-threshold swing remains sub-60mV/dec over 1.5 orders of magnitude of current at room temperature. The EOT of the devices is 0.8nm, which plays a major role in achieving the desired sub-60 mV/dec performance.

“We have entered an era where new chip technologies require making trade-offs between power, performance, cost and area. And these trade-offs will be considered separately for different application domains,” says Nadine Collaert, distinguished member of technical staff at imec. “TFETs will most probably find their place in the ultralow-power segment. Many applications in the future require transistors to work at low power and low voltage, such as the many Internet of Things applications.

At CS International, imec’s expert Nadine Collaert will discuss the progress made and challenges ahead in processing TFETs, focusing on the materials and integration, but also on the impact of using TFETs in electronic circuits.

“Advanced substrates are the key interconnect component of advanced packaging architectures,” says Andrej Ivankovic, Technology & Market Analyst, Advanced Packaging & Semiconductor Manufacturing at Yole Développement (Yole). Indeed advanced substrates are critical in enabling future products and markets.

To answer to technology evolution and market needs, Yole’s advanced packaging team has established a stand-alone dedicated advanced substrate activity, focused on exploring the market and technologies of PCBs, package substrates and RDLs. And today, the “More than Moore” market research and strategy consulting company announces its first report titled “Advanced Substrates Overview: From IC Package to Board”. This technology & market analysis serves as an overview of advanced substrate technologies, markets, and supply chain, to be supported by subsequent in-depth reports.

advanced substrate tech

Advanced substrates are a key enabler of future products and markets. Yole’s analysts offer you a special focus on this industry and its competitive landscape.

Today’s advanced substrates in volume are:
• FC substrates
• 2.5D/3D TSV assemblies
• And thin-film RDLs especially for FOWLP advanced packaging platform, below an L/S resolution of 15/15 um and with transition below L/S < 10/10 um.

These advanced substrates are traditionally linked to higher-end logic such as CPUs /GPUs, DSPs , etc. Driven by ICs in the latest technology nodes in the computing, networking, mobile, and high-end consumer market segments (gaming, HD /Smart TV).

Moreover, due to additional form factor and low power demands, WLP and advanced FC substrates are also widespread in majority of smartphone functions. Yole’s analysts identified: application processors, baseband, transceivers, filters, amplifiers, WiFi modules, drivers, codecs, power management, etc.

Future higher-end products will require package substrates with L/S < 10/10 um and boards with L/S < 30/30 um. These demands have given rise to three distinct competition areas:
• Board vs. IC substrate (See the image 1: green & grey zone)
• IC substrate vs. FOWLP (See the image 1: green & orange zone)
• FOWLP vs. 2.5D/3D packaging (See the image 1: yellow & orange zone)

The board vs. FC substrate area is characterized by the transition from the subtractive to the mSAP process, and competition between board and substrate manufacturers. Evaluation of “substrate-like PCBs” is already under way at OEMs, and so too the potential new integration opportunities they could bring. Furthermore, developments in FC substrate, FOWLP, and 2.5D/3D packaging have created an immense competitive arena for L/S < 10/10 um packaging, with a large variety of solutions coming from business models across the supply chain including IDMs, foundries, OSATs, WLP houses, substrate manufacturers, and EMS.

As shown in figure 2, the transition to substrates for ICs below L/S < 10/10 um has begun, led by application processors/basebands in FOWLP and advanced FC substrates, and the first GPUs in 2.5D/3D TSV configuration. The “below L/S < 10/10 um” advanced substrate roadmap is open, with intense R&D underway and each manufacturer developing strategies and targets for their respective solutions….

Yole’s advanced substrates report is an overview of the technology status and market evolution. It will be followed by further in-depth reports. Today, with this first edition, the objective is to provide an overview of board, substrate and RDL interconnects, analyze the technology trends and assess future development of the advanced substrate market. A detailed description of the report is available on i-micronews.com, Advanced Packaging reports section.

The Fan-Out platform’s excitement has clearly caught the attention of the advanced packaging industry as well as advanced substrate manufacturers. Day to day, Yole’s advanced packaging team is enlarging its know-how to understand the technical and economic issues.
Analysts are daily interacting with advanced packaging leaders to turn research results into strategies and define a long-term view of the business.
To point out its commitment towards the advanced packaging community, Yole is playing a key role within the program of the 13th International Conference and Exhibition on Device Packaging (March 6-9, 2017 – Fountain Hills, Arizona USA). The consulting company announces two presentations on March 7:
• What is driving the 3D TSV technologies business? Santosh Kumar, Sr Technology & Market Analyst, Yole
• FOWLP: market & technology trend. Jérôme Azemar, Technology & Market Analyst, Yole

As well as a panel discussion titled “The Fan-Out Breakout” moderated by Jérôme Azemar. Fan-Out is the most dynamic solution in the advanced packaging playground at the moment. Make sure you will get an up-to-date vision of the market and debate with brilliant panelists including:

• Rich Rice, Sr. VP of Business Development, ASE Global
• Islam Salama, Director, Pathfinding Department, Substrate and Packaging Technology Development at Intel
• Johannes Lodermeyer, Wafer Level Technology Development Responsible, Infineon Technologies
• Vinayak Pandey, Product and Technology Marketing Director / Scott Sikorski, Product Technology Marketing Vice-President at JCET / STATS ChipPAC
• And Santosh Kumar, Sr Technology & Market Analyst, Yole

Dream Chip Technologies announced today the presentation of the industry`s first 22nm FD-SOI silicon for a new ADAS System-on-Chip (SoC) for automotive computer vision applications at the Mobile World Congress in Barcelona. The SoC was created in close cooperation with ARM, Arteris, Cadence, GLOBALFOUNDRIES, and INVECAS as part of the European Commission’s ENIAC THINGS2DO reference development platform.

The SoC offers high performance image acquisition and processing capabilities and supports convolutional neural network (CNN) vision workloads to meet the demand for complex automotive object detection and processing.  This ADAS SoC is highly optimized for high-end computer vision performance at a very low-power consumption to enable autonomous driving in production and is capable to support ADAS functions like road-sign recognition, lane departure warning, driver distraction warning, blind spot detection, surround vision, park assist, pedestrian detection, cruise control and emergency braking.”

The design incorporates Dream Chip Technologies’ image signal processing pipeline in conjunction with Cadence Tensilica Vision P6 DSPs and a quad-core cluster of ARM® Cortex®-A53 processors. In addition, a lock-step pair of Cortex-R5 processors provides ISO 26262 compliant functional safety and the SoC is interconnected with an Arteris FlexNoC network-on-chip. The SoC uses multiple IPs such as foundation IPs, LPDDR4, PLL, Thermal Sensor and Process Monitor, from INVECAS. Cadence’s LPDDR4 controller and INVECAS’ LPDDR4 PHY IP provide two LPDDR4 3200 high bandwidth memory interfaces.

Dr. Jens Benndorf, Managing Director and Co-Founder of DCT said: “It was a unique experience to create and coordinate such a powerful team and successfully lead the consortium to two tape-outs. In this project, we have delivered silicon using a brand new process technology for the automotive industry.” He adds: “The project not only shows the strength of the European semiconductor industry, but also an ability to collaborate efficiently to provide technology needed urgently by the industry to power advanced automated driving solutions.”

Dream Chip Technologies has designed many highly complex SoCs for customers worldwide and was selected as the design service lead for this THINGS2DO project. The project has created a camera-based ADAS reference platform which benefits automotive companies through advanced technology and by shortening design cycles and time-to-market for automotive innovation. The SoC is fabricated on GF’s 22FDX® semiconductor process at the foundry’s Fab 1 facility in Dresden, Germany.

The new ADAS platform is targeted at automotive Tier-1s with a need for cost, performance and power-optimized SoCs for a range of ADAS applications and with potential for customization.

The choice of a quad-core Cortex-A53 processor configuration is a popular choice for computer vision applications to manage automotive vision applications. More advanced autonomous driving systems can also be enabled with this level of computer vision capability, including those using multiple smart cameras.

“This project provides a boost for European chip designers focused on solving some of the automotive world’s most complex problems,” said Nandan Nayampally, general manager, CPU Group, ARM. “By using a quad-core ARM Cortex-A53 configuration, with the Cortex-R5 fortifying the safety critical aspects, Dream Chip has produced a highly efficient and functionally safe processing solution that sets a high bar in the automotive vision sector. It underlines the rapidly increasingly deployment of ARM technology in vehicles; ranging from detection sensors to infotainment, ADAS and autonomous driving.”

“ADAS features are exhibiting the highest growth within the automotive electronics domain as vehicle makers look to differentiate on enhanced products that provide real-time vision processing,” said Rajeev Rajan, vice president of IoT and Automotive at GF. “GF’s 22FDX is an ideal platform to design power- and performance-efficient solutions for automotive vision and camera ADAS applications. As an industry first, this milestone affirms our commitment to support and collaboratively shape automotive markets.”

Dasaradha Gude, CEO of INVECAS said: “We are excited to contribute to this program as this collaboration further strengthens INVECAS’ position as a key provider of silicon proven IPs for GLOBALFOUNDRIES’ 22FDX technology. INVECAS’ rich family of IP offerings ranging from Foundation IP, Interface IP like Multiprotocol SerDes, DDR34/LPDDR34, MIPI, HDMI etc. enables complex SoC designs for the automotive market addressing the next wave of connected car opportunities in Europe. Our objective is to provide silicon-proven IP and ASIC solutions to address the challenges of ever growing design complexity faced by the semiconductor industry today.”

GlobalFoundries_Ajit_ManochSEMI, the global association connecting and representing the worldwide electronics manufacturing supply chain, today announced the appointment of Ajit Manocha as its president and CEO. He will succeed Denny McGuirk, who announced his intention to retire last October. The SEMI International Board of Directors conducted a comprehensive search process, selecting Manocha, an industry leader with over 35 years of global experience in the semiconductor industry.  Manocha will begin his new role on March 1 at SEMI’s new Milpitas headquarter offices.

“Ajit has a deep understanding of our industry’s dynamics and the interdependence of the electronics manufacturing supply chain,” said Y.H. Lee, chairman of SEMI’s board of directors. “From his early days developing dry etch processes at AT&T Bell Labs, to running global manufacturing for Philips/NXP, Spansion, and, as CEO of GLOBALFOUNDRIES, Ajit has been formative to our industry’s growth. Ajit is the ideal choice to drive our SEMI 2020 plan and beyond, ensuring that SEMI provides industry stewardship and engages its members to advance the interests of the global electronics manufacturing supply chain.”

“Beyond his experience leading some of our industry’s top fabs, Ajit has long been active at SEMI and has served on boards of several global associations and consortia,” said Denny McGuirk, retiring president and CEO of SEMI. “Ajit’s experience in technology, manufacturing, and industry stewardship is a powerful combination. I’m very excited to be passing the baton to Ajit as he will continue to advance the growth and prosperity of SEMI’s members.”

“I have tremendous respect for the work SEMI does on behalf of the industry,” said Ajit Manocha, incoming president and CEO of SEMI. “I am excited to be joining SEMI at a time when our ecosystem is rapidly expanding due to extensive innovation on several fronts.  From applications based on the Internet and the growth of mobile devices to artificial intelligence/machine learning, autonomous vehicles, and the Internet of Things, there is a much broader scope for SEMI to foster heterogeneous collaboration and fuel growth today than ever before.  I am looking forward to leading the global SEMI organization as we strive to maximize value for our members across this extended global ecosystem.”

Manocha was formerly CEO at GLOBALFOUNDRIES, during which he also served as vice chairman and chairman of the Semiconductor Industry Association (SIA).  Earlier, Manocha served as EVP of worldwide operations at Spansion. Prior to Spansion, he was EVP and chief manufacturing officer at Philips/NXP Semiconductors. Manocha also held senior management positions within AT&T Microelectronics. He began his career at AT&T Bell Laboratories as a research scientist where he was granted several patents related to microelectronics manufacturing. Manocha holds a bachelor’s degree from the University of Delhi and a master’s degree in physical chemistry from Kansas State University.

3D processing at Tohoku U


February 20, 2017

BY PHIL GARROU, Contributing Editor

At the recent IEEE 3DIC Conference, Koyanagi and co-workers at Tohoku Univ reported on their studies of Ti as a 3D TSV barrier layer.

Cu was substituted in the early 2000s for Al inter- connect wiring which no longer meet the resistivity requirements in the aggressively scaled technology nodes. Cu, which has low electrical resistivity has proved itself as a potential interconnect material, only if necessary barrier layers are in place.

The most serious concern with Cu as interconnect material is the formation of midgap defects in active Si, since it diffuses fast into the Si. Owing to this, the minority carrier life time is reduced several orders even at 200 °C. Moreover, during this diffusion process since Cu travels through SiO2, the insulation nature of SiO2 is degraded which can result in premature dielectric breakdown leading to device failure. The well-known method to prevent Cu diffusing into SiO2 and then in Si is to sandwich an amorphous metal layer between the Cu and SiO2. Required properties of a good barrier layer are low internal film stress, high thermal stability and low resistivity. Metals with high melting points are known to have larger activation energy for the diffusion to take place.

Although Ta is best suited as a barrier material based on melting point, Ta has more integrated film stress than Ti film, i.e. a 200nm-thick sputtered Ta film possesses internal stress of 1.4 GPa, whereas the stress in a similar thickness Ti film is 0.8 GPa . Internal stress is the main cause for the delamination of sputtered Ta films. Thus Ti is a better barrier layer based on internal stress.
One way to improve the barrier performance of Ti, is to use a Ti/TiN structure as barrier layer, but TiN has a large resistivity (p~270 μ.cm) .

The Tohoku group has found a simple method to improve the barrier ability of Ti layer is to anneal the TSV structures in vacuum at temperatures up to 400°C. This results in a significant improvement in leakage current characteristics for SiO2 dielectric. TiSix has been identified at the interface between Cu and SiO2 during the sputter deposition.

Another presentation by Tohoku University examined the reduction of the keep-out-zone in 3DIC by local stress suppression with negative-CTE filler.

The thinning of the IC chips leads to low flexural rigidity of IC chips. In addition, the CTE of the underfill material is larger than that of metal microbumps. In other words, the underfill material shrinks more compared to metal microbumps. IC chips are bent by this shrinkage after the 3D integration process. This CTE mismatch induces local bending stress in thinned Si chips, and in turn effects the MOSFET electrical performance in thinned Si chips.

In general, SiO2 or Al2O3 filler have been introduced into the underfill to reduce the CTE of underfill. High density filler is required to realize a CTE close to the value of the microbumps.

However, it is difficult to use the conventional density underfill for 3D IC with fine pitch microbumps due to its high viscosity. What’s required is a low viscosity low CTE underfill.
The Tohoku group suggests a negative CTE material as the filler to suppress the local bending stress. They used manganese nitride-based negative-CTE material as filler. The CTE of this material is -45 ppm/K at the temperature from 65 °C to 100 °C.