Category Archives: 3D Integration

Invensas Corporation, a wholly owned subsidiary of Tessera Holding Corporation (Nasdaq: TSRA), today announced that Teledyne DALSA, a Teledyne Technologies company, has signed a technology transfer and license agreement for Direct Bond Interconnect (DBI) technology. This agreement enables Teledyne DALSA to leverage Invensas’ revolutionary semiconductor wafer bonding and 3D interconnect technologies to deliver next-generation MEMS and image sensor solutions to customers in the automotive, IoT and consumer electronics markets. Teledyne DALSA is an international leader in high performance digital imaging and semiconductors and also one of the world’s foremost pure-play MEMS foundries.

“DBI technology is a key enabler for true 3D-integrated MEMS and image sensor solutions,” said Edwin Roks, president of Teledyne DALSA. “We are excited about the prospect of developing new products and providing new foundry services to our customers that utilize this technology. By working closely with Invensas, we will be able to move more quickly to deploy this capability efficiently and effectively.”

DBI technology is a low temperature hybrid wafer bonding solution that allows wafers to be bonded instantaneously with exceptionally fine pitch 3D electrical interconnect without requiring bond pressure. The technology is applicable to a wide range of semiconductor devices including MEMS, image sensors, RF Front Ends and stacked memory.

“We are pleased that Teledyne DALSA, a recognized leader in digital imaging products and MEMS solutions, has chosen our DBI technology to accelerate the development and commercialization of their next generation MEMS and image sensor products,” said Craig Mitchell, president of Invensas. “As device makers look for increasingly powerful semiconductor solutions in smaller packages, the need for cost-efficient, versatile 3D technologies is greater than ever before. We are confident that the superior performance and manufacturability of DBI technology will help Teledyne DALSA deliver tremendous value to their customers.”

GE Ventures and Samsung Electro-Mechanics (SEMCO) announced today a multi-year, worldwide patent license agreement. With this partnership, SEMCO will license GE microelectronics packaging patent portfolio, covering the fabrication of substrates embedded with electronic circuits.

Developed by GE Global Research and Imbera Electronics Oy (now GE Embedded Electronics Oy) as part of a major GE focus in power electronics research over the last decade, the patent portfolio is of particular value for high performance communication and mobility products.

“GE is extremely pleased that SEMCO has recognized the significance of GE’s IP in this space,” says Lawrence Davis, Vice President and MicroElectronics Packaging Program Director at GE Ventures. “As the demand for increased power efficiency and higher performance in mobility products continues to expand, GE is positioned to be a strong partner for embedded electronics technology in the power and consumer electronics space.”

GE Ventures accelerates innovation and growth for partners by providing access to GE technologies through licensing and joint development partnerships. This advanced microelectronics packaging technology is being licensed to leading global manufacturing partners to provide advanced solutions to businesses worldwide.

By Paula Doe, SEMI

The explosive growth in demand for internet bandwidth and cloud computing capacity brings a new set of technology challenges and opportunities for the semiconductor supply chain. “Azure grew by 2X last year, but we can’t pull more performance out of the existing architecture,” noted Kushagra Vaid, Microsoft’s GM Hardware Engineering, Cloud & Enterprise, at last week’s Linley Cloud Hardware Conference in Santa Clara, Calif.  “We are at a junction point where we have to evolve the architecture of the last 20-30 years.” He stressed that the traditional way of designing chips and systems to optimize for particular workloads isn’t working anymore. “We can’t design for a workload so huge and diverse. It’s not clear what part of it runs on any one machine,” he noted. “How do you know what to optimize? Past benchmarks are completely irrelevant.”

Explosive growth in demand for data storage and processing in the cloud means change across the chip world. Source: Cisco VNI Global IP Traffic Forecast

Explosive growth in demand for data storage and processing in the cloud means change across the chip world. Source: Cisco VNI Global IP Traffic Forecast

Roadmap accelerates for networking chips 

Look for accelerating change in the networking chip market. Now that merchant chip suppliers have taken over 75 percent of the networking chip market from the proprietary suppliers, intense competition has meant astonishing improvements in reducing size and power, and two-year technology cycles, reported keynote speaker Andreas Bechtolsheim, Arista Networks Chief Development Officer and Chairman.  “The cloud is accelerating transitions, as the big data centers demand low cost,” he noted, explaining that new technologies no longer see gradual adoption through different applications. They have to start out cheaper to get any traction at all, but then ramp sharply to high volume in six months as high-volume data centers convert.

Data center networks expect transition to 400G to start in 2018. Source: MACOM

Data center networks expect transition to 400G to start in 2018. Source: MACOM

Bechtolsheim said the majority of the network link market will convert from 40G to 100G this year, and to 400G in 2019.  For 800G two years later, chip design will have to start this year. Luckily there’s a clear path for scaling on the chip side, from the current generation’s 28nm technology down to 16nm and 7nm.  But it could be a push for some of the ecosystem. “It’s pushing the packaging vendors, as 1.0mm solder balls are about the limit,” said Bechtolsheim. Companies are also forming a group to speed the standards process by making the 800G standard simply 2X that for 400G, as the 400B standard took eight years.

The 40G chips at the server layer are moving to pulse amplitude modulation (PAM4) to send and receive four signals at once, which will require moving to digital signal processing. Moving from analog bipolar to digital CMOS technology also enables significant scaling of chip size and power, with significant reduction in die area (~50 percent) and power (~40 percent) with 16nm FinFET compared to 28nm, noted MACOM’s Chris Collins, director of Marketing. The company plans 7nm 800G devices next year.

New layers and new types of memory

One likely change is new types and new placement for memory, for higher speeds, different levels of non-volatile cache, and designs and accelerator subsystems that limit the need to move large amounts of data back and forth over limited pipelines. “Data is doubling every 2-2.5 years, but DRAM bandwidth is only doubling every 5 years. It’s not keeping up,” noted Steven Woo, Rambus VP, Systems and Solutions. “We’ll see the addition of more tiers of memory over the next few years.” He suggested the emerging challenge would be what data to place where, using what technology, and how to move memory in general closer to the processing. Racks may become the basic unit instead of servers, so each can be optimized with more memory or more processors as needed.

Handling big data in the cloud means more opportunity for new memory technologies in an emerging tier between DRAM and solid state drives. Source: Rambus

Handling big data in the cloud means more opportunity for new memory technologies in an emerging tier between DRAM and solid state drives. Source: Rambus

Specialized accelerators speed particular applications

Another emerging solution is specialized chips or subsystem boards to accelerate particular types of cloud processing by taking over some jobs from the CPU cores, typically with different types of processors and lots of localized memory. Google and Wave Computing have their accelerator chips optimized for neural network processing. Mellanox offers offload adopter cards based on ASICs, FPGAs or RISC, with increasingly complex functions, claiming the potential to offload as much as of 80 percent of the overhead function of the CPU, to get a 2.7X increase in throughput per server.  MoSys proposes replacing conventional content addressable memory with a programmable search engine, based on an FPGA, a lot of SRAM, and software to search and route with different strategies for different types of applications to significantly increase speeds. Chelsio offers a module to handle encryption and decryption off the CPU without having to shuttle information back and forth to memory. Amazon even is renting FPGAs in its cloud so users can design their own accelerators for their particular workloads. But Microsoft’s Vaid remained skeptical that a proliferation of solutions for particular applications would be the best approach for the general use in the cloud.

300mm production and passive fiber alignment improve silicon photonics

Silicon photonics technology continues to make progress, and may find application in the market for very high bandwidth, mid to long haul transmission (30 meters to 80 kilometer), where spectral efficiency is the key driver, suggested Ted Letavic, Global Foundries, Senior Fellow. “4.5 and 5G communications will use photonics solutions similar to those needed in the data center, for volume that will drive down cost,” he noted. The foundry has now transferred its monolithic process to 300mm wafers, where the immersion lithography enables better overlay and line edge roughness, to reduce losses by 3X.  The company has an automated, passive solution to attach the optical fiber to the edge of the chip, pushing ribbons of multiple fibers into MEMS groves in the chip with an automated pick and place tool.  Letavic said the edge coupling process was in production for a telecommunications application.

Array of optical fibers are passively aligned by sliding into MEMS grooves at the side of the chip for 100Gpbs x 12 = 1.2Tb interconnect in flat form factor. Source: Global Foundries

Array of optical fibers are passively aligned by sliding into MEMS grooves at the side of the chip for 100Gpbs x 12 = 1.2Tb interconnect in flat form factor. Source: Global Foundries

For more information about SEMI, visit www.semi.org. SEMI also offers many events covering electronics manufacturing supply chain issues; for a full list of SEMI events, visit www.semi.org/en/events. SEMI is on LinkedIn and Twitter.

Research and Markets has announced the addition of the “3D IC and 2.5D IC Packaging Market by Application (Logic, Imaging & Optoelectronics, Memory, MEMS/Sensors, LED, Power), Packaging Technology (3D Wafer-Level Chip-Scale Packaging, 3D TSV, 2.5D), End-User Industry, and Region – Global Forecast to 2022” report to their offering.

The market is expected to be worth USD 170.46 billion in 2022, at a CAGR of 38.30% between 2016 and 2022.

The drivers for this market are the increasing need for advanced architecture in electronic products, rising trend of miniaturization of electronic devices, and growing market for tablets, smartphones, and gaming devices. The main restraint for this market is created by the thermal issues caused by higher levels of integration.

The 3D TSV market is expected to grow at the highest CAGR during the forecast period. The major factors driving the 3D IC and 2.5D IC packaging market for 3D TSV include highest interconnect density and greater space efficiencies in 3D TSV compared to all other types of advanced packaging such as 3D WLCSP and 2.5 D.

The demand for 3D IC and 2.5D IC packages in logic is growing because of the high product availability. An increasing number of manufacturers in this market offer innovative products with advanced packaging. For instance, Intel Corp. (U.S.) is driving the market for advanced packaging in field programmable gate arrays (FPGA). Global companies started introducing 3D logic ICs in different programmable logics to ensure operational efficiency with added convenience and increased productivity.

The market in APAC is expected to grow at the highest CAGR because there is a high demand for 3D IC and 2.5D IC packaging technology from the growing consumer electronics sector in this region, particularly for smartphones and tablets. The presence of major 3D IC and 2.5D IC packaging manufacturers and suppliers in this region helps to decrease the time to market for 3D IC and 2.5D IC packaging products. This makes the integration of 3D IC and 2.5D IC packaging technology in the APAC region much easier.

GLOBALFOUNDRIES yesterday announced plans to expand its global manufacturing footprint in response to growing customer demand for its comprehensive and differentiated technology portfolio. The company is investing in its existing leading-edge fabs in the United States and Germany, expanding its footprint in China with a fab in Chengdu, and adding capacity for mainstream technologies in Singapore.

“We continue to invest in capacity and technology to meet the needs of our worldwide customer base,” said GF CEO Sanjay Jha. “We are seeing strong demand for both our mainstream and advanced technologies, from our world-class RF-SOI platform for connected devices to our FD-SOI and FinFET roadmap at the leading edge. These new investments will allow us to expand our existing fabs while growing our presence in China through a partnership in Chengdu.”

In the United States, GF plans to expand 14nm FinFET capacity by an additional 20 percent at its Fab 8 facility in New York, with the new production capabilities to come online in the beginning of 2018. This expansion builds on the approximately $13 billion invested in the United States over the last eight years, with an associated 9,000 direct jobs across four locations and 15,000 jobs within the regional ecosystem. New York will continue to be the center of leading-edge technology development for 7nm and extreme ultraviolet (EUV) lithography, with 7nm production planned for Q2 2018.

In Germany, GF plans to build up 22FDX 22nm FD-SOI capacity at is Fab 1 facility in Dresden to meet demand for the Internet of Things (IoT), smartphone processors, automotive electronics, and other battery-powered wirelessly connected applications, growing the overall fab capacity by 40 percent by 2020. Dresden will continue to be the center for FDX technology development. GF engineers in Dresden are already developing the company’s next-generation 12FDX technology, with customer product tape-outs expected to begin in the middle of 2018.

In China, GF and the Chengdu municipality have formed a partnership to build a fab in Chengdu. The partners plan to establish a 300mm fab to support the growth of the Chinese semiconductor market and to meet accelerating global customer demand for 22FDX. The fab will begin production of mainstream process technologies in 2018 and then focus on manufacturing GF’s commercially available 22FDX process technology, with volume production expected to start in 2019.

In Singapore, GF will increase 40nm capacity at its 300mm fab by 35 percent, while also enabling more 180nm production on its 200mm manufacturing lines. The company will also add new capabilities to produce its industry-leading RF-SOI technology.

“GF has had a strong foundry relationship with Qualcomm Technologies for many years across a wide range of process nodes,” said Roawen Chen, senior vice president, QCT global operations, Qualcomm Technologies, Inc. “We are excited to see GF making these new investments in differentiated technology and expanding global capacity to support Qualcomm Technologies in delivering the next wave of innovation across a range of integrated circuits that support our business.”

“Collaborative foundry partnerships are critical for us to differentiate ourselves in the competitive market for mobile SoCs,” said Min Li, chief executive officer of Rockchip. “We are pleased to see GF bringing its innovative 22FDX technology to China and investing in the capacity necessary to support the country’s growing fabless semiconductor industry.”

“As our customers increasingly demand more from their mobile experiences, the need for a strong manufacturing partner is greater than ever,” said Joe Chen, co-chief operating officer of MediaTek. “We are thrilled to have a partner like GF that invests in the global capacity we need to deliver powerful and efficient mobile technologies for markets ranging from networking and connectivity to the Internet of Things.”

Grant A. Pierce, chief executive officer (CEO) of Sonics, Inc., supplier of on-chip network (NoC) and power management technologies and services, was elected by the Board of Directors of the Electronic System Design Alliance (ESD Alliance) to serve as its chairman.

“It is an honor and a privilege to be named chairman of the ESD Alliance by my peers on the board,” remarks Pierce. “This is a great opportunity to help guide the organization through the transformation it began in 2016 to broaden its focus to system issues encompassing hardware, software, and design. My experience at Sonics straddling both the system-on-chip IP hardware and design software businesses should serve as a strong unifying asset in this leadership role on the board.”

In a related move, Bob Smith, executive director of the ESD Alliance, joined the board of directors as part of a recent amendment that updated the ESD Alliance bylaws to reflect the broader mission of the organization.

Other board members are:

  • Aart de Geus, chairman and CEO of Synopsys, Inc.
  • Dean Drako, president and CEO at IC Manage
  • Amit Gupta, president and CEO from Solido Design Automation
  • John Kibarian, president, CEO and co-founder of PDF Solutions, Inc.
  • Lucio Lanza, managing director at Lanza techVentures
  • Walden C. Rhines, chairman and CEO from Mentor Graphics Corporation
  • Simon Segars, ARM’s CEO
  • Lip-Bu Tan, president and CEO of Cadence Design Systems

“I’m pleased with the board’s selection of Grant Pierce to chair our organization,” says Smith. “He is an active board member, whose varied industry experience and well-honed skillset will help us forge ahead. He and I had the opportunity to work together on several projects and I welcome the chance to work more closely with him.”

Grant A. Pierce, a co-founder of Sonics, Inc., was elected to the ESD Alliance (formerly the EDA Consortium) Board of Directors in 2014 and will serve as chairman until the next board elections in 2018. He has served as Sonics’ CEO and president and as chairman of the board of directors since 1997. Over the earlier part of his more than 30-year career in high technology, Pierce served in senior management roles in a wide range of companies that built digital media and communications devices, object-oriented software development environments, fabless semiconductors, mini-computer systems, and peripherals. Pierce is a former certified public accountant and began his career with Arthur Andersen and Co.

Intel Corporation yesterday announced plans to invest more than $7 billion to complete Fab 42, a project Intel had previously started and then left vacant. The high-volume factory is in Chandler, Ariz., and is targeted to use the 7 nanometer (nm) manufacturing process. The announcement was made by U.S. President Donald Trump and Intel CEO Brian Krzanich at the White House.

Intel Corporation on Tuesday, Feb. 8, 2017, announced plans to invest more than $7 billion to complete Fab 42. On completion, Fab 42 in Chandler, Ariz., is expected to be the most advanced semiconductor factory in the world. (Credit: Intel Corporation)

Intel Corporation on Tuesday, Feb. 8, 2017, announced plans to invest more than $7 billion to complete Fab 42. On completion, Fab 42 in Chandler, Ariz., is expected to be the most advanced semiconductor factory in the world. (Credit: Intel Corporation)

According to Intel’s official press release, the completion of Fab 42 in 3 to 4 years will directly create approximately 3,000 high-tech, high-wage Intel jobs for process engineers, equipment technicians, and facilities-support engineers and technicians who will work at the site. Combined with the indirect impact on businesses that will help support the factory’s operations, Fab 42 is expected to create more than 10,000 total long-term jobs in Arizona.

Mr. Trump said of the announcement: “The people of Arizona will be very happy. It’s a lot of jobs.”

There will be no incentives from the federal government for the Intel project, the White House said.

Context for the investment was outlined in an e-mail from Intel’s CEO to employees.

“Intel’s business continues to grow and investment in manufacturing capacity and R&D ensures that the pace of Moore’s law continues to march on, fueling technology innovations the world loves and depends on,” said Krzanich. “This factory will help the U.S. maintain its position as the global leader in the semiconductor industry.”

“Intel is a global manufacturing and technology company, yet we think of ourselves as a leading American innovation enterprise,” Krzanich added. “America has a unique combination of talent, a vibrant business environment and access to global markets, which has enabled U.S. companies like Intel to foster economic growth and innovation. Our factories support jobs — high-wage, high-tech manufacturing jobs that are the economic engines of the states where they are located.”

Intel is America’s largest high-technology capital expenditure investor ($5.1 billion in the U.S. 2015) and its third largest investor in global R&D ($12.1 billion in 20151). The majority of Intel’s manufacturing and R&D is in the United States. As a result, Intel employs more than 50,000 people in the United States, while directly supporting almost half a million other U.S. jobs across a range of industries, including semiconductor tooling, software, logistics, channels, OEMs and other manufacturers that incorporate our products into theirs.

The 7nm semiconductor manufacturing process targeted for Fab 42 will be the most advanced semiconductor process technology used in the world and represents the future of Moore’s Law. In 1968, Intel co-founder Gordon Moore predicted that computing power will become significantly more capable and yet cost less year after year.

The chips made on the 7nm process will power the most sophisticated computers, data centers, sensors and other high-tech devices, and enable things like artificial intelligence, more advanced cars and transportation services, breakthroughs in medical research and treatment, and more. These are areas that depend upon having the highest amount of computing power, access to the fastest networks, the most data storage, the smallest chip sizes, and other benefits that come from advancing Moore’s Law.

After the announcement, President Trump tweeted his thanks to Krzanich, calling the factory a great investment in jobs and innovation. In his email to employees, Krzanich said that he had chosen to announce the expansion at the White House to “level the global playing field and make U.S. manufacturing competitive worldwide through new regulatory standards and investment policies.”

“When we disagree, we don’t walk away,” he wrote. “We believe that we must be part of the conversation to voice our views on key issues such as immigration, H1B visas and other policies that are essential to innovation.”

During Mr. Trump’s presidential campaign, Krzanich had reportedly planned a Trump fundraiser event and then cancelled following numerous controversial statements from Trump regarding his proposed immigration policies. Intel has continued to be critical of the Trump administration’s immigration policies, joining over 100 other companies to file a legal brief challenging President Trump’s January 27 executive order which blocked entry of all refugees and immigrants from seven predominantly Muslim countries. Recently, Krzanich took to Twitter to criticize the order, voicing the company’s support of lawful immigration.

In 2012, Paul Otellini, then Intel’s CEO, made a similar promise about Fab 42 in the company of Obama, during a visit to Hillsboro, Oregon.

IC Insights’ 20th anniversary, 2017 edition of The McClean Report shows that since 2010, worldwide economic growth has been the primary influencer of IC industry growth.  In this “global economy-driven” IC industry, factors such as interest rates, oil prices, and fiscal stimulus are the primary drivers of IC market growth.  This is much different than prior to 2010, when capital spending, IC industry capacity, and IC pricing characteristics drove IC industry cycles.

Figure 1 plots the actual annual growth rates for worldwide GDP and the IC market from 1992 and includes IC Insights’ 2017 forecast.  As shown, both of these categories displayed extremely volatile behavior from 1992 through 2010 before registering much more subdued growth rates from 2011 through 2016.  Moreover, IC Insights forecasts similar restrained annual growth rates for worldwide GDP and the IC market through 2021.

Figure 1

Figure 1

Some observations regarding worldwide economic growth (GDP) include the following.

•    Since 1980, the annual worldwide GDP growth has averaged 2.8%. The average annual worldwide GDP growth rate has declined every decade since the 1960s with a slight rebound forecast to be registered in the first seven years of the current decade.

•    Worldwide GDP growth of 2.5% or less is currently considered by most economists to be indicative of a global recession, which puts 2016’s growth right at the threshold.  The 2017 global growth rate is forecast to come in only slightly better at 2.6%.  Prior to the late 1990s, when emerging markets like China and India represented a much smaller share of the worldwide economy, a global recession was typically defined as 2.0% or less growth.  The global recession threshold has never been a “hard and fast” rule, but the guidelines discussed here are useful for this analysis.

Figure 2 compares the actual annual growth rates of worldwide GDP and the worldwide IC market from 2011 through IC Insights’ 2017 forecast.  It is worth mentioning that the same scale used in Figure 1 for both worldwide GDP growth (-2% to 5%) and IC market growth (-40% to 50%) was used for this chart.  It is clear when looking at this specific timeperiod and using the historical growth rate scale end points, that IC market and worldwide GDP growth volatility from 2011 through 2017 is expected to be much more tame than in the past.

Figure 2

Figure 2

Worldwide GDP growth rates are expected to range from 2.5% to 3.0% from 2016 through 2021.  IC Insights’ expects the IC market to mirror the narrow range of worldwide GDP growth with forecasted growth rates ranging from a low of 2% to a high of 7% through 2021.

Given the tight correlation between annual worldwide GDP growth rates and IC market growth rates, IC Insights believes that a significant and noticeable IC market cycle will not occur through 2021 unless there is a significant departure from trend, up or down, for worldwide GDP growth (e.g., <2% growth on the low side and >3.0% growth on the high side).

Nexperia, the former Standard Products division of NXP, today announced the formal completion of its launch as a separate entity. Headquartered in Nijmegen, Netherlands and backed by a consortium of financial investors consisting of Beijing Jianguang Asset Management Co. Ltd and Wise Road Capital Ltd, Nexperia is a stand-alone, world-class leader in discretes, logic and MOSFETs, retaining all the expertise, manufacturing resources and key personnel of the former NXP division, while bringing a new focus and powerful commitment to these product areas.

Nexperia, which will produce around 85 billion devices a year and in 2016 had revenues exceeding US$1.1B, addresses three key trends: power efficiency; protection and filtering; and miniaturization. The Automotive sector is very strong for Nexperia and mostof its products are AECQ101 qualified. Other important markets include portable devices, industrial, communications infrastructure, consumer and computing. A significant portion of the company’s revenue is delivered through distribution channels.

Nexperia CEO Frans Scheper, formerly EVP and GM of NXP’s Standard Products Business Unit, comments: “Our history ensures that Nexperia is already regarded as a strong industry leader in discretes, logic and MOSFETs, which consistently delivers highly reliable and innovative products to our global customers. Under the new ownership and with a renewed sense of vigour we will invest in product development and best-in-class manufacturing practices and facilities to ensure that Nexperia becomes the byword for efficiency and quality. Together with our engaged and motivated employees this will enable us on a daily basis to exceed the needs and expectations of our customers.”

Nexperia has two front-end manufacturing facilities, in Manchester, UK and Hamburg, Germany, and three back-end packaging plants in Guangdong, China, Seremban, Malaysia and Cabuyao, Philippines. It currently employs about 11,000 personnel worldwide including an established and successful leadership team. Scheper continues: “Because Nexperia will continue to source its front end and back end production from its current manufacturing sites, there will be no disruption in our supply chain or other processes, so customers and partners can be fully assured that they will continue to receive excellent products and exceptional service.”

The company has an extensive IP portfolio and is certified to ISO9001, ISO/TS16949, ISO14001 and OHSAS18001.

Toshiba America Electronic Components, Inc. (TAEC) has added a new photorelay to its extensive lineup of photocouplers. Housed in the Toshiba-developed S-VSON4, the industry’s smallest package, the new TLP3406S is suited for use in automatic test equipment, measuring instruments, high-speed logic IC testers, high-speed memory testers, and probe cards.

Semiconductor testers and other applications are pushing photorelays to support higher temperatures in a smaller package size. Toshiba has answered the call with its new TLP3406S. The upper end of the TLP3406S’s operating range is 110°C (max.), which is up from 85°C (max.) in previous offerings.  In spite of its small package size, the TLP3406S features a very small on-resistance and on/off switching of currents as high as 1.5A, enabling it to be used for switching applications in high-speed testers.

The use of Toshiba’s S-VSON4 package reduces the mounting area by approximately 22.5 percent when compared to larger VSON4 packages. This reduction in size will enable the development of smaller test boards, and can increase density by allowing for the inclusion of more photorelays on a board.